| # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| $id: http://devicetree.org/schemas/interrupt-controller/mstar,mst-intc.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| title: MStar Interrupt Controller |
| - Mark-PK Tsai <mark-pk.tsai@mediatek.com> |
| MStar, SigmaStar and Mediatek TV SoCs contain multiple legacy |
| interrupt controllers that routes interrupts to the GIC. |
| The HW block exposes a number of interrupt controllers, each |
| can support up to 64 interrupts. |
| interrupt-controller: true |
| Use the same format as specified by GIC in arm,gic.yaml. |
| The range <start, end> of parent interrupt controller's interrupt |
| lines that are hardwired to mstar interrupt controller. |
| $ref: /schemas/types.yaml#/definitions/uint32-matrix |
| Mark this controller has no End Of Interrupt(EOI) implementation. |
| additionalProperties: false |
| mst_intc0: interrupt-controller@1f2032d0 { |
| compatible = "mstar,mst-intc"; |
| interrupt-parent = <&gic>; |
| mstar,irqs-map-range = <0 63>; |