| // SPDX-License-Identifier: GPL-2.0 |
| * (C) Copyright 2017 Rockchip Electronics Co., Ltd |
| #include <asm/arch-rockchip/clock.h> |
| #include <asm/arch-rockchip/cru_rk3328.h> |
| #include <asm/arch-rockchip/hardware.h> |
| int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type) |
| struct sysreset_reg *offset = dev_get_priv(dev); |
| unsigned long cru_base = (unsigned long)rockchip_get_cru(); |
| if (IS_ERR_VALUE(cru_base)) |
| writel(0xeca8, cru_base + offset->glb_srst_snd_value); |
| writel(0xfdb9, cru_base + offset->glb_srst_fst_value); |
| static struct sysreset_ops rockchip_sysreset = { |
| .request = rockchip_sysreset_request, |
| U_BOOT_DRIVER(sysreset_rockchip) = { |
| .name = "rockchip_sysreset", |
| .ops = &rockchip_sysreset, |