| // SPDX-License-Identifier: GPL-2.0+ |
| * (C) Copyright 2014 - 2015 Xilinx, Inc. |
| * Michal Simek <michal.simek@xilinx.com> |
| * (This file derived from arch/arm/mach-zynqmp/cpu.c) |
| * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved. |
| #include <asm/armv8/mmu.h> |
| /* size: IO + NR_DRAM_BANKS + terminator */ |
| struct mm_region tegra_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = { |
| .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | |
| PTE_BLOCK_PXN | PTE_BLOCK_UXN |
| .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | |
| struct mm_region *mem_map = tegra_mem_map; |