dts/upstream/src/arm64/freescale/fsl-ls1046a-qds.dts

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Device Tree Include file for Freescale Layerscape-1046A family SoC.
 *
 * Copyright 2016 Freescale Semiconductor, Inc.
 * Copyright 2018-2019 NXP
 *
 * Shaohui Xie <Shaohui.Xie@nxp.com>
 */

/dts-v1/;

#include "fsl-ls1046a.dtsi"

/ {
	model = "LS1046A QDS Board";
	compatible = "fsl,ls1046a-qds", "fsl,ls1046a";

	aliases {
		emi1-slot1 = &ls1046mdio_s1;
		emi1-slot2 = &ls1046mdio_s2;
		emi1-slot4 = &ls1046mdio_s4;
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		gpio2 = &gpio2;
		gpio3 = &gpio3;
		qsgmii-s2-p1 = &qsgmii_phy_s2_p1;
		qsgmii-s2-p2 = &qsgmii_phy_s2_p2;
		qsgmii-s2-p3 = &qsgmii_phy_s2_p3;
		qsgmii-s2-p4 = &qsgmii_phy_s2_p4;
		serial0 = &duart0;
		serial1 = &duart1;
		serial2 = &duart2;
		serial3 = &duart3;
		sgmii-s1-p1 = &sgmii_phy_s1_p1;
		sgmii-s1-p2 = &sgmii_phy_s1_p2;
		sgmii-s1-p3 = &sgmii_phy_s1_p3;
		sgmii-s1-p4 = &sgmii_phy_s1_p4;
		sgmii-s4-p1 = &sgmii_phy_s4_p1;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};
};

&dspi {
	bus-num = <0>;
	status = "okay";

	flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "n25q128a11", "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;
	};

	flash@1 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "sst25wf040b", "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <1>;
		spi-max-frequency = <10000000>;
	};

	flash@2 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "en25s64", "jedec,spi-nor";
		spi-cpol;
		spi-cpha;
		reg = <2>;
		spi-max-frequency = <10000000>;
	};
};

&duart0 {
	status = "okay";
};

&duart1 {
	status = "okay";
};

&i2c0 {
	status = "okay";

	i2c-mux@77 {
		compatible = "nxp,pca9547";
		reg = <0x77>;
		#address-cells = <1>;
		#size-cells = <0>;

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x2>;

			ina220@40 {
				compatible = "ti,ina220";
				reg = <0x40>;
				shunt-resistor = <1000>;
			};

			ina220@41 {
				compatible = "ti,ina220";
				reg = <0x41>;
				shunt-resistor = <1000>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0x3>;

			rtc@51 {
				compatible = "nxp,pcf2129";
				reg = <0x51>;
				/* IRQ10_B */
				interrupts = <0 150 0x4>;
			};

			eeprom@56 {
				compatible = "atmel,24c512";
				reg = <0x56>;
			};

			eeprom@57 {
				compatible = "atmel,24c512";
				reg = <0x57>;
			};

			temp-sensor@4c {
				compatible = "adi,adt7461a";
				reg = <0x4c>;
			};
		};
	};
};

&ifc {
	#address-cells = <2>;
	#size-cells = <1>;
	/* NOR, NAND Flashes and FPGA on board */
	ranges = <0x0 0x0 0x0 0x60000000 0x08000000
		  0x1 0x0 0x0 0x7e800000 0x00010000
		  0x2 0x0 0x0 0x7fb00000 0x00000100>;
	status = "okay";

	nor@0,0 {
		compatible = "cfi-flash";
		reg = <0x0 0x0 0x8000000>;
		big-endian;
		bank-width = <2>;
		device-width = <1>;
	};

	nand@1,0 {
		compatible = "fsl,ifc-nand";
		reg = <0x1 0x0 0x10000>;
	};

	fpga: board-control@2,0 {
		compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
		reg = <0x2 0x0 0x0000100>;
		ranges = <0 2 0 0x100>;
	};
};

&lpuart0 {
	status = "okay";
};

&qspi {
	status = "okay";

	qflash0: flash@0 {
		compatible = "spansion,m25p80";
		#address-cells = <1>;
		#size-cells = <1>;
		spi-max-frequency = <50000000>;
		spi-rx-bus-width = <4>;
		spi-tx-bus-width = <4>;
		reg = <0>;
	};
};

#include "fsl-ls1046-post.dtsi"

&fman0 {
	ethernet@e0000 {
		phy-handle = <&qsgmii_phy_s2_p1>;
		phy-connection-type = "sgmii";
	};

	ethernet@e2000 {
		phy-handle = <&sgmii_phy_s4_p1>;
		phy-connection-type = "sgmii";
	};

	ethernet@e4000 {
		phy-handle = <&rgmii_phy1>;
		phy-connection-type = "rgmii";
	};

	ethernet@e6000 {
		phy-handle = <&rgmii_phy2>;
		phy-connection-type = "rgmii";
	};

	ethernet@e8000 {
		phy-handle = <&sgmii_phy_s1_p3>;
		phy-connection-type = "sgmii";
	};

	ethernet@ea000 {
		phy-handle = <&sgmii_phy_s1_p4>;
		phy-connection-type = "sgmii";
	};

	ethernet@f0000 { /* DTSEC9/10GEC1 */
		phy-handle = <&sgmii_phy_s1_p1>;
		phy-connection-type = "xgmii";
	};

	ethernet@f2000 { /* DTSEC10/10GEC2 */
		phy-handle = <&sgmii_phy_s1_p2>;
		phy-connection-type = "xgmii";
	};
};

&fpga {
	#address-cells = <1>;
	#size-cells = <1>;

	mdio-mux-emi1 {
		compatible = "mdio-mux-mmioreg", "mdio-mux";
		mdio-parent-bus = <&mdio0>;
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x54 1>;    /* BRDCFG4 */
		mux-mask = <0xe0>; /* EMI1 */

		/* On-board RGMII1 PHY */
		ls1046mdio0: mdio@0 {
			reg = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			rgmii_phy1: ethernet-phy@1 { /* MAC3 */
				reg = <0x1>;
			};
		};

		/* On-board RGMII2 PHY */
		ls1046mdio1: mdio@1 {
			reg = <0x20>;
			#address-cells = <1>;
			#size-cells = <0>;

			rgmii_phy2: ethernet-phy@2 { /* MAC4 */
				reg = <0x2>;
			};
		};

		/* Slot 1 */
		ls1046mdio_s1: mdio@2 {
			reg = <0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sgmii_phy_s1_p1: ethernet-phy@1c {
				reg = <0x1c>;
			};

			sgmii_phy_s1_p2: ethernet-phy@1d {
				reg = <0x1d>;
			};

			sgmii_phy_s1_p3: ethernet-phy@1e {
				reg = <0x1e>;
			};

			sgmii_phy_s1_p4: ethernet-phy@1f {
				reg = <0x1f>;
			};
		};

		/* Slot 2 */
		ls1046mdio_s2: mdio@3 {
			reg = <0x60>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			qsgmii_phy_s2_p1: ethernet-phy@8 {
				reg = <0x8>;
			};

			qsgmii_phy_s2_p2: ethernet-phy@9 {
				reg = <0x9>;
			};

			qsgmii_phy_s2_p3: ethernet-phy@a {
				reg = <0xa>;
			};

			qsgmii_phy_s2_p4: ethernet-phy@b {
				reg = <0xb>;
			};
		};

		/* Slot 4 */
		ls1046mdio_s4: mdio@5 {
			reg = <0x80>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";

			sgmii_phy_s4_p1: ethernet-phy@1c {
				reg = <0x1c>;
			};
		};
	};
};