include/configs/MPC837XERDB.h - filogic/uboot - Gitiles

 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2007 Freescale Semiconductor, Inc.
  * Kevin Lam <kevin.lam@freescale.com>
  * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
  */

 #ifndef __CONFIG_H
 #define __CONFIG_H

 #include <linux/stringify.h>

 /*
  * High Level Configuration Options
  */

 #define CONFIG_HWCONFIG

 /*
  * On-board devices
  */
 #define CONFIG_VSC7385_ENET

 /* System performance - define the value i.e. CONFIG_SYS_XXX
 */

 /* System Clock Configuration Register */
 #define CONFIG_SYS_SCCR_TSEC1CM	1		/* eTSEC1 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_TSEC2CM	1		/* eTSEC2 clock mode (0-3) */
 #define CONFIG_SYS_SCCR_SATACM	SCCR_SATACM_2	/* SATA1-4 clock mode (0-3) */

 /*
  * System IO Config
  */
 #define CONFIG_SYS_SICRH		0x08200000
 #define CONFIG_SYS_SICRL		0x00000000

 /*
  * Output Buffer Impedance
  */
 #define CONFIG_SYS_OBIR		0x30100000

 /*
  * Device configurations
  */

 /* Vitesse 7385 */

 #ifdef CONFIG_VSC7385_ENET

 #define CONFIG_TSEC2

 /* The flash address and size of the VSC7385 firmware image */
 #define CONFIG_VSC7385_IMAGE		0xFE7FE000
 #define CONFIG_VSC7385_IMAGE_SIZE	8192

 #endif

 /*
  * DDR Setup
  */
 #define CONFIG_SYS_SDRAM_BASE		0x00000000 /* DDR is system memory */
 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	0x03000000
 #define CONFIG_SYS_83XX_DDR_USES_CS0

 #define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)

 #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU	/* Never assert ODT to internal IOs */

 /*
  * Manually set up DDR parameters
  */
 #define CONFIG_SYS_DDR_SIZE		256		/* MB */
 #define CONFIG_SYS_DDR_CS0_BNDS		0x0000000f
 #define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
 					| CSCONFIG_ODT_WR_ONLY_CURRENT \
 					| CSCONFIG_ROW_BIT_13 \
 					| CSCONFIG_COL_BIT_10)

 #define CONFIG_SYS_DDR_TIMING_3	0x00000000
 #define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
 				| (0 << TIMING_CFG0_WRT_SHIFT) \
 				| (0 << TIMING_CFG0_RRT_SHIFT) \
 				| (0 << TIMING_CFG0_WWT_SHIFT) \
 				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
 				| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
 				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
 				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
 				/* 0x00260802 */ /* DDR400 */
 #define CONFIG_SYS_DDR_TIMING_1	((3 << TIMING_CFG1_PRETOACT_SHIFT) \
 				| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
 				| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
 				| (7 << TIMING_CFG1_CASLAT_SHIFT) \
 				| (13 << TIMING_CFG1_REFREC_SHIFT) \
 				| (3 << TIMING_CFG1_WRREC_SHIFT) \
 				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
 				| (2 << TIMING_CFG1_WRTORD_SHIFT))
 				/* 0x3937d322 */
 #define CONFIG_SYS_DDR_TIMING_2	((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
 				| (5 << TIMING_CFG2_CPO_SHIFT) \
 				| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
 				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
 				| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
 				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
 				| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
 				/* 0x02984cc8 */

 #define CONFIG_SYS_DDR_INTERVAL	((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
 				| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
 				/* 0x06090100 */

 #define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
 					| SDRAM_CFG_SDRAM_TYPE_DDR2)
 					/* 0x43000000 */
 #define CONFIG_SYS_DDR_SDRAM_CFG2	0x00001000 /* 1 posted refresh */
 #define CONFIG_SYS_DDR_MODE		((0x0406 << SDRAM_MODE_ESD_SHIFT) \
 					| (0x0442 << SDRAM_MODE_SD_SHIFT))
 					/* 0x04400442 */ /* DDR400 */
 #define CONFIG_SYS_DDR_MODE2		0x00000000

 /*
  * Memory test
  */
 #undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */

 /*
  * The reserved memory
  */

 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef	CONFIG_SYS_RAMBOOT
 #endif

 #define CONFIG_SYS_MONITOR_LEN	(512 * 1024) /* Reserve 512 kB for Mon */

 /*
  * Initial RAM Base Address Setup
  */
 #define CONFIG_SYS_INIT_RAM_LOCK	1
 #define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
 #define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

 /*
  * FLASH on the Local Bus
  */
 #define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
 #define CONFIG_SYS_FLASH_SIZE		8 /* max FLASH size is 32M */

 #define CONFIG_SYS_FLASH_EMPTY_INFO		/* display empty sectors */


 #define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */

 #undef	CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
 #define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

 /*
  * NAND Flash on the Local Bus
  */
 #define CONFIG_SYS_NAND_BASE	0xE0600000


 /* Vitesse 7385 */

 #define CONFIG_SYS_VSC7385_BASE	0xF0000000

 /*
  * Serial Port
  */
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

 #define CONFIG_SYS_BAUDRATE_TABLE \
 		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

 /* SERDES */
 #define CONFIG_FSL_SERDES
 #define CONFIG_FSL_SERDES1	0xe3000
 #define CONFIG_FSL_SERDES2	0xe3100

 /* I2C */
 #define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }

 /*
  * Config on-board RTC
  */
 #define CONFIG_RTC_DS1374	/* use ds1374 rtc via i2c */
 #define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */

 /*
  * General PCI
  * Addresses are mapped 1-1.
  */
 #define CONFIG_SYS_PCI_MEM_BASE		0x80000000
 #define CONFIG_SYS_PCI_MEM_PHYS		CONFIG_SYS_PCI_MEM_BASE
 #define CONFIG_SYS_PCI_MEM_SIZE		0x10000000 /* 256M */
 #define CONFIG_SYS_PCI_MMIO_BASE	0x90000000
 #define CONFIG_SYS_PCI_MMIO_PHYS	CONFIG_SYS_PCI_MMIO_BASE
 #define CONFIG_SYS_PCI_MMIO_SIZE	0x10000000 /* 256M */
 #define CONFIG_SYS_PCI_IO_BASE		0x00000000
 #define CONFIG_SYS_PCI_IO_PHYS		0xE0300000
 #define CONFIG_SYS_PCI_IO_SIZE		0x100000 /* 1M */

 #define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
 #define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000

 #define CONFIG_SYS_PCIE1_BASE		0xA0000000
 #define CONFIG_SYS_PCIE1_CFG_BASE	0xA0000000
 #define CONFIG_SYS_PCIE1_CFG_SIZE	0x08000000
 #define CONFIG_SYS_PCIE1_MEM_BASE	0xA8000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xA8000000
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
 #define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xB8000000
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

 #define CONFIG_SYS_PCIE2_BASE		0xC0000000
 #define CONFIG_SYS_PCIE2_CFG_BASE	0xC0000000
 #define CONFIG_SYS_PCIE2_CFG_SIZE	0x08000000
 #define CONFIG_SYS_PCIE2_MEM_BASE	0xC8000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xC8000000
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x10000000
 #define CONFIG_SYS_PCIE2_IO_BASE	0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xD8000000
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00800000

 #ifdef CONFIG_PCI
 #undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
 #endif	/* CONFIG_PCI */

 /*
  * TSEC
  */
 #ifdef CONFIG_TSEC_ENET

 #define CONFIG_GMII			/* MII PHY management */

 #define CONFIG_TSEC1

 #ifdef CONFIG_TSEC1
 #define CONFIG_TSEC1_NAME		"TSEC0"
 #define CONFIG_SYS_TSEC1_OFFSET		0x24000
 #define TSEC1_PHY_ADDR			2
 #define TSEC1_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC1_PHYIDX			0
 #endif

 #ifdef CONFIG_TSEC2
 #define CONFIG_TSEC2_NAME		"TSEC1"
 #define CONFIG_SYS_TSEC2_OFFSET		0x25000
 #define TSEC2_PHY_ADDR			0x1c
 #define TSEC2_FLAGS			(TSEC_GIGABIT | TSEC_REDUCED)
 #define TSEC2_PHYIDX			0
 #endif
 #endif

 /*
  * SATA
  */
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1_OFFSET	0x18000
 #define CONFIG_SYS_SATA1	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
 #define CONFIG_SYS_SATA1_FLAGS	FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2_OFFSET	0x19000
 #define CONFIG_SYS_SATA2	(CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
 #define CONFIG_SYS_SATA2_FLAGS	FLAGS_DMA

 #ifdef CONFIG_FSL_SATA
 #define CONFIG_LBA48
 #endif

 /*
  * Environment
  */

 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

 #ifdef CONFIG_MMC
 #define CONFIG_FSL_ESDHC_PIN_MUX
 #define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC83xx_ESDHC_ADDR
 #endif

 /*
  * Miscellaneous configurable options
  */

 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 256 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

 /*
  * Environment Configuration
  */

 #define CONFIG_HAS_FSL_DR_USB
 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET

 #define CONFIG_NETDEV		"eth1"

 #define CONFIG_HOSTNAME		"mpc837x_rdb"
 #define CONFIG_ROOTPATH		"/nfsroot"
 				/* U-Boot image on TFTP server */
 #define CONFIG_UBOOTPATH	"u-boot.bin"
 #define CONFIG_FDTFILE		"mpc8379_rdb.dtb"

 #define CONFIG_EXTRA_ENV_SETTINGS \
 	"netdev=" CONFIG_NETDEV "\0"				\
 	"uboot=" CONFIG_UBOOTPATH "\0"					\
 	"tftpflash=tftp $loadaddr $uboot;"				\
 		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
 			" +$filesize; "	\
 		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
 			" +$filesize; "	\
 		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
 			" $filesize; "	\
 		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
 			" +$filesize; "	\
 		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
 			" $filesize\0"	\
 	"fdtaddr=780000\0"						\
 	"fdtfile=" CONFIG_FDTFILE "\0"					\
 	"ramdiskaddr=1000000\0"						\
 	"ramdiskfile=rootfs.ext2.gz.uboot\0"				\
 	"console=ttyS0\0"						\
 	"setbootargs=setenv bootargs "					\
 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
 	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
 		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
 							"$netdev:off "	\
 		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"

 #endif	/* __CONFIG_H */
	/* SPDX-License-Identifier: GPL-2.0+ */
	/*
	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	* Kevin Lam <kevin.lam@freescale.com>
	* Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
	*/

	#ifndef __CONFIG_H
	#define __CONFIG_H

	#include <linux/stringify.h>

	/*
	* High Level Configuration Options
	*/

	#define CONFIG_HWCONFIG

	/*
	* On-board devices
	*/
	#define CONFIG_VSC7385_ENET

	/* System performance - define the value i.e. CONFIG_SYS_XXX
	*/

	/* System Clock Configuration Register */
	#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
	#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
	#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */

	/*
	* System IO Config
	*/
	#define CONFIG_SYS_SICRH 0x08200000
	#define CONFIG_SYS_SICRL 0x00000000

	/*
	* Output Buffer Impedance
	*/
	#define CONFIG_SYS_OBIR 0x30100000

	/*
	* Device configurations
	*/

	/* Vitesse 7385 */

	#ifdef CONFIG_VSC7385_ENET

	#define CONFIG_TSEC2

	/* The flash address and size of the VSC7385 firmware image */
	#define CONFIG_VSC7385_IMAGE 0xFE7FE000
	#define CONFIG_VSC7385_IMAGE_SIZE 8192

	#endif

	/*
	* DDR Setup
	*/
	#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */
	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
	#define CONFIG_SYS_83XX_DDR_USES_CS0

	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \| DDRCDR_ODT \| DDRCDR_Q_DRN)

	#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */

	/*
	* Manually set up DDR parameters
	*/
	#define CONFIG_SYS_DDR_SIZE 256 /* MB */
	#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
	\| CSCONFIG_ODT_WR_ONLY_CURRENT \
	\| CSCONFIG_ROW_BIT_13 \
	\| CSCONFIG_COL_BIT_10)

	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	\| (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
	/* 0x00260802 / / DDR400 */
	#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
	\| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	\| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
	\| (7 << TIMING_CFG1_CASLAT_SHIFT) \
	\| (13 << TIMING_CFG1_REFREC_SHIFT) \
	\| (3 << TIMING_CFG1_WRREC_SHIFT) \
	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
	/* 0x3937d322 */
	#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
	\| (5 << TIMING_CFG2_CPO_SHIFT) \
	\| (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	\| (3 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	\| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
	/* 0x02984cc8 */

	#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
	\| (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
	/* 0x06090100 */

	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
	\| SDRAM_CFG_SDRAM_TYPE_DDR2)
	/* 0x43000000 */
	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
	#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
	\| (0x0442 << SDRAM_MODE_SD_SHIFT))
	/* 0x04400442 / / DDR400 */
	#define CONFIG_SYS_DDR_MODE2 0x00000000

	/*
	* Memory test
	*/
	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */

	/*
	* The reserved memory
	*/

	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	#define CONFIG_SYS_RAMBOOT
	#else
	#undef CONFIG_SYS_RAMBOOT
	#endif

	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */

	/*
	* Initial RAM Base Address Setup
	*/
	#define CONFIG_SYS_INIT_RAM_LOCK 1
	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

	/*
	* FLASH on the Local Bus
	*/
	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
	#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */

	#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */


	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */

	#undef CONFIG_SYS_FLASH_CHECKSUM
	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */

	/*
	* NAND Flash on the Local Bus
	*/
	#define CONFIG_SYS_NAND_BASE 0xE0600000


	/* Vitesse 7385 */

	#define CONFIG_SYS_VSC7385_BASE 0xF0000000

	/*
	* Serial Port
	*/
	#define CONFIG_SYS_NS16550_SERIAL
	#define CONFIG_SYS_NS16550_REG_SIZE 1
	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)

	#define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)

	/* SERDES */
	#define CONFIG_FSL_SERDES
	#define CONFIG_FSL_SERDES1 0xe3000
	#define CONFIG_FSL_SERDES2 0xe3100

	/* I2C */
	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }

	/*
	* Config on-board RTC
	*/
	#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */

	/*
	* General PCI
	* Addresses are mapped 1-1.
	*/
	#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
	#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
	#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
	#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
	#define CONFIG_SYS_PCI_IO_BASE 0x00000000
	#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
	#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */

	#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
	#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
	#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000

	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
	#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000

	#define CONFIG_SYS_PCIE2_BASE 0xC0000000
	#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
	#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
	#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
	#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
	#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000

	#ifdef CONFIG_PCI
	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	#endif /* CONFIG_PCI */

	/*
	* TSEC
	*/
	#ifdef CONFIG_TSEC_ENET

	#define CONFIG_GMII /* MII PHY management */

	#define CONFIG_TSEC1

	#ifdef CONFIG_TSEC1
	#define CONFIG_TSEC1_NAME "TSEC0"
	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	#define TSEC1_PHY_ADDR 2
	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	#define TSEC1_PHYIDX 0
	#endif

	#ifdef CONFIG_TSEC2
	#define CONFIG_TSEC2_NAME "TSEC1"
	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	#define TSEC2_PHY_ADDR 0x1c
	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	#define TSEC2_PHYIDX 0
	#endif
	#endif

	/*
	* SATA
	*/
	#define CONFIG_SATA1
	#define CONFIG_SYS_SATA1_OFFSET 0x18000
	#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
	#define CONFIG_SATA2
	#define CONFIG_SYS_SATA2_OFFSET 0x19000
	#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA

	#ifdef CONFIG_FSL_SATA
	#define CONFIG_LBA48
	#endif

	/*
	* Environment
	*/

	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */

	#ifdef CONFIG_MMC
	#define CONFIG_FSL_ESDHC_PIN_MUX
	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
	#endif

	/*
	* Miscellaneous configurable options
	*/

	/*
	* For booting Linux, the board info and command line data
	* have to be in the first 256 MB of memory, since this is
	* the maximum mapped by the Linux kernel during initialization.
	*/
	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */

	/*
	* Environment Configuration
	*/

	#define CONFIG_HAS_FSL_DR_USB
	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

	#define CONFIG_NETDEV "eth1"

	#define CONFIG_HOSTNAME "mpc837x_rdb"
	#define CONFIG_ROOTPATH "/nfsroot"
	/* U-Boot image on TFTP server */
	#define CONFIG_UBOOTPATH "u-boot.bin"
	#define CONFIG_FDTFILE "mpc8379_rdb.dtb"

	#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" CONFIG_NETDEV "\0" \
	"uboot=" CONFIG_UBOOTPATH "\0" \
	"tftpflash=tftp $loadaddr $uboot;" \
	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	" +$filesize; " \
	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	" +$filesize; " \
	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	" $filesize; " \
	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	" +$filesize; " \
	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	" $filesize\0" \
	"fdtaddr=780000\0" \
	"fdtfile=" CONFIG_FDTFILE "\0" \
	"ramdiskaddr=1000000\0" \
	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
	"console=ttyS0\0" \
	"setbootargs=setenv bootargs " \
	"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	"$netdev:off " \
	"root=$rootdev rw console=$console,$baudrate $othbootargs\0"

	#endif /* __CONFIG_H */