| * This is Altera's synthesizable logic block I2C Controller for use |
| - compatible : should be "altr,softip-i2c-v1.0" |
| - reg : Offset and length of the register set for the device |
| - interrupts : <IRQ> where IRQ is the interrupt number. |
| - clocks : phandle to input clock. |
| - clock-frequency : desired I2C bus clock frequency in Hz. |
| - fifo-size : Size of the RX and TX FIFOs in bytes. |
| - Child nodes conforming to i2c bus binding |
| compatible = "altr,softip-i2c-v1.0"; |
| reg = <0x00000001 0x00080000 0x00000040>; |
| interrupt-parent = <&intc>; |
| clock-frequency = <100000>; |
| compatible = "atmel,24c32"; |