| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/ |
| * |
| * Author: Robert Nelson <robertcnelson@gmail.com> |
| */ |
| |
| / { |
| cpus { |
| cpu@0 { |
| cpu0-supply = <&dcdc2_reg>; |
| }; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 0x20000000>; /* 512 MB */ |
| }; |
| }; |
| |
| &cpu0_opp_table { |
| /* |
| * Octavo Systems: |
| * The EFUSE_SMA register is not programmed for any of the AM335x wafers |
| * we get and we are not programming them during our production test. |
| * Therefore, from a DEVICE_ID revision point of view, the silicon looks |
| * like it is Revision 2.1. However, from an EFUSE_SMA point of view for |
| * the HW OPP table, the silicon looks like it is Revision 1.0 (ie the |
| * EFUSE_SMA register reads as all zeros). |
| */ |
| opp-1000000000 { |
| /* OPP Nitro */ |
| opp-supported-hw = <0x06 0x0100>; |
| }; |
| }; |
| |
| &am33xx_pinmux { |
| i2c0_pins: pinmux-i2c0-pins { |
| pinctrl-single,pins = < |
| AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0) |
| AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0) |
| >; |
| }; |
| }; |
| |
| &i2c0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&i2c0_pins>; |
| |
| status = "okay"; |
| clock-frequency = <400000>; |
| |
| tps: tps@24 { |
| reg = <0x24>; |
| }; |
| }; |
| |
| /include/ "../../tps65217.dtsi" |
| |
| &tps { |
| interrupts = <7>; /* NMI */ |
| interrupt-parent = <&intc>; |
| |
| ti,pmic-shutdown-controller; |
| |
| pwrbutton { |
| interrupts = <2>; |
| status = "okay"; |
| }; |
| |
| regulators { |
| dcdc1_reg: regulator@0 { |
| regulator-name = "vdds_dpr"; |
| regulator-always-on; |
| }; |
| |
| dcdc2_reg: regulator@1 { |
| /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ |
| regulator-name = "vdd_mpu"; |
| regulator-min-microvolt = <925000>; |
| regulator-max-microvolt = <1351500>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| dcdc3_reg: regulator@2 { |
| /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ |
| regulator-name = "vdd_core"; |
| regulator-min-microvolt = <925000>; |
| regulator-max-microvolt = <1150000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo1_reg: regulator@3 { |
| regulator-name = "vio,vrtc,vdds"; |
| regulator-always-on; |
| }; |
| |
| ldo2_reg: regulator@4 { |
| regulator-name = "vdd_3v3aux"; |
| regulator-always-on; |
| }; |
| |
| ldo3_reg: regulator@5 { |
| regulator-name = "vdd_1v8"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-always-on; |
| }; |
| |
| ldo4_reg: regulator@6 { |
| regulator-name = "vdd_3v3a"; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| |
| &aes { |
| status = "okay"; |
| }; |
| |
| &sham { |
| status = "okay"; |
| }; |