| // SPDX-License-Identifier: GPL-2.0+ |
| * dts file for Xilinx ZynqMP ZC1254 |
| * (C) Copyright 2015 - 2018, Xilinx, Inc. |
| * Michal Simek <michal.simek@xilinx.com> |
| * Siva Durga Prasad Paladugu <sivadur@xilinx.com> |
| #include "zynqmp-clk-ccf.dtsi" |
| model = "ZynqMP ZC1254 RevA"; |
| compatible = "xlnx,zynqmp-zc1254-revA", "xlnx,zynqmp-zc1254", "xlnx,zynqmp"; |
| stdout-path = "serial0:115200n8"; |
| reg = <0x0 0x0 0x0 0x80000000>; |
| compatible = "m25p80", "jedec,spi-nor"; /* 32MB */ |
| spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */ |
| spi-max-frequency = <108000000>; /* Based on DC1 spec */ |
| partition@qspi-fsbl-uboot { /* for testing purpose */ |
| label = "qspi-fsbl-uboot"; |
| partition@qspi-linux { /* for testing purpose */ |
| reg = <0x100000 0x500000>; |
| partition@qspi-device-tree { /* for testing purpose */ |
| label = "qspi-device-tree"; |
| reg = <0x600000 0x20000>; |
| partition@qspi-rootfs { /* for testing purpose */ |
| reg = <0x620000 0x5E0000>; |