| commit | 4dae96b24524a8b233c331201b1189b2ce9494a2 | [log] [tgz] |
|---|---|---|
| author | Tom Warren <twarren@nvidia.com> | Wed Apr 03 14:39:30 2013 -0700 |
| committer | Tom Warren <twarren@nvidia.com> | Mon Apr 15 11:01:38 2013 -0700 |
| tree | 5bdef44cb41f3818fec6d5741654bba1348ef19a | |
| parent | fbef3559708999da8a805b1898ce5c9866acfc56 [diff] |
Tegra: Fix MSELECT clock divisors for T30/T114. A comparison of registers between our internal NV U-Boot and u-boot-tegra/next showed some discrepancies in the MSELECT clock divisor programming. T20 doesn't have a MSELECT clk src reg. Signed-off-by: Tom Warren <twarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com>