tree 5bdef44cb41f3818fec6d5741654bba1348ef19a
parent fbef3559708999da8a805b1898ce5c9866acfc56
author Tom Warren <twarren@nvidia.com> 1365025170 -0700
committer Tom Warren <twarren@nvidia.com> 1366048898 -0700

Tegra: Fix MSELECT clock divisors for T30/T114.

A comparison of registers between our internal NV U-Boot and
u-boot-tegra/next showed some discrepancies in the MSELECT
clock divisor programming. T20 doesn't have a MSELECT clk src reg.

Signed-off-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>