Gitiles
Code Review
Sign In
git01.mediatek.com
/
filogic
/
uboot
/
4b4ef68fda1f5b7954b55a174d19baf7c8536d9b
/
.
/
board
/
freescale
/
t4rdb
/
t4_rcw.cfg
blob: fdbbe5ef6593b25b43b068bedf7f2b01d3a662bf [
file
] [
log
] [
blame
]
#PBL preamble and RCW header
aa55aa55
010e0100
#serdes protocol 27_56_1_9
16070019
18101916
00000000
00000000
6c700848
00448c00
6c020000
f5000000
00000000
ee0000ee
00000000
000287fc
00000000
50000000
00000000
00000028