arch/powerpc/dts/p4080.dtsi

// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
 * P4080/P4040 Silicon/SoC Device Tree Source (pre include)
 *
 * Copyright 2011 - 2015 Freescale Semiconductor Inc.
 * Copyright 2019 NXP
 */

/dts-v1/;

/include/ "e500mc_power_isa.dtsi"

/ {
	compatible = "fsl,P4080";
	#address-cells = <2>;
	#size-cells = <2>;
	interrupt-parent = <&mpic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: PowerPC,e500mc@0 {
			device_type = "cpu";
			reg = <0>;
			fsl,portid-mapping = <0x80000000>;
		};
		cpu1: PowerPC,e500mc@1 {
			device_type = "cpu";
			reg = <1>;
			fsl,portid-mapping = <0x40000000>;
		};
		cpu2: PowerPC,e500mc@2 {
			device_type = "cpu";
			reg = <2>;
			fsl,portid-mapping = <0x20000000>;
		};
		cpu3: PowerPC,e500mc@3 {
			device_type = "cpu";
			reg = <3>;
			fsl,portid-mapping = <0x10000000>;
		};
		cpu4: PowerPC,e500mc@4 {
			device_type = "cpu";
			reg = <4>;
			fsl,portid-mapping = <0x08000000>;
		};
		cpu5: PowerPC,e500mc@5 {
			device_type = "cpu";
			reg = <5>;
			fsl,portid-mapping = <0x04000000>;
		};
		cpu6: PowerPC,e500mc@6 {
			device_type = "cpu";
			reg = <6>;
			fsl,portid-mapping = <0x02000000>;
		};
		cpu7: PowerPC,e500mc@7 {
			device_type = "cpu";
			reg = <7>;
			fsl,portid-mapping = <0x01000000>;
		};
	};

	soc: soc@ffe000000 {
		ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
		reg = <0xf 0xfe000000 0 0x00001000>;
		#address-cells = <1>;
		#size-cells = <1>;
		device_type = "soc";
		compatible = "simple-bus";

		mpic: pic@40000 {
			interrupt-controller;
			#address-cells = <0>;
			#interrupt-cells = <4>;
			reg = <0x40000 0x40000>;
			compatible = "fsl,mpic", "chrp,open-pic";
			device_type = "open-pic";
			clock-frequency = <0x0>;
		};
	};
};