| CONFIG_ARM=y |
| CONFIG_SYS_CONFIG_NAME="xilinx_zynqmp_zc1751_xm018_dc4" |
| CONFIG_ARCH_ZYNQMP=y |
| CONFIG_SYS_MALLOC_F_LEN=0x8000 |
| CONFIG_IDENT_STRING=" Xilinx ZynqMP ZC1751 xm018 dc4" |
| CONFIG_SYS_TEXT_BASE=0x8000000 |
| CONFIG_DEFAULT_DEVICE_TREE="zynqmp-zc1751-xm018-dc4" |
| CONFIG_FIT=y |
| CONFIG_FIT_VERBOSE=y |
| CONFIG_SPL_LOAD_FIT=y |
| CONFIG_SPL=y |
| CONFIG_SPL_SYS_MALLOC_SIMPLE=y |
| CONFIG_HUSH_PARSER=y |
| CONFIG_SYS_PROMPT="ZynqMP> " |
| # CONFIG_CMD_IMLS is not set |
| CONFIG_CMD_MEMTEST=y |
| # CONFIG_CMD_FLASH is not set |
| CONFIG_CMD_MMC=y |
| CONFIG_CMD_I2C=y |
| CONFIG_CMD_TFTPPUT=y |
| CONFIG_CMD_DHCP=y |
| CONFIG_CMD_MII=y |
| CONFIG_CMD_PING=y |
| CONFIG_CMD_TIME=y |
| CONFIG_CMD_TIMER=y |
| CONFIG_CMD_EXT2=y |
| CONFIG_CMD_EXT4=y |
| CONFIG_CMD_EXT4_WRITE=y |
| CONFIG_CMD_FAT=y |
| CONFIG_CMD_FS_GENERIC=y |
| CONFIG_SPL_OF_CONTROL=y |
| CONFIG_OF_EMBED=y |
| CONFIG_NET_RANDOM_ETHADDR=y |
| CONFIG_SPL_DM=y |
| CONFIG_SPL_DM_SEQ_ALIAS=y |
| CONFIG_BLK=y |
| CONFIG_FPGA_XILINX=y |
| CONFIG_FPGA_ZYNQMPPL=y |
| CONFIG_DM_GPIO=y |
| CONFIG_DM_I2C=y |
| CONFIG_SYS_I2C_CADENCE=y |
| CONFIG_DM_MMC=y |
| CONFIG_DM_MMC_OPS=y |
| CONFIG_ZYNQ_SDHCI=y |
| CONFIG_DM_ETH=y |
| CONFIG_ZYNQ_GEM=y |
| CONFIG_DEBUG_UART=y |
| CONFIG_DEBUG_UART_ZYNQ=y |
| CONFIG_DEBUG_UART_BASE=0xff000000 |
| CONFIG_DEBUG_UART_CLOCK=100000000 |
| CONFIG_DEBUG_UART_ANNOUNCE=y |