arch/arm/dts/stm32mp15-scmi-u-boot.dtsi

// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2022 - All Rights Reserved
 */

/ {
	aliases {
		gpio0 = &gpioa;
		gpio1 = &gpiob;
		gpio2 = &gpioc;
		gpio3 = &gpiod;
		gpio4 = &gpioe;
		gpio5 = &gpiof;
		gpio6 = &gpiog;
		gpio7 = &gpioh;
		gpio8 = &gpioi;
		gpio9 = &gpioj;
		gpio10 = &gpiok;
		gpio25 = &gpioz;
		pinctrl0 = &pinctrl;
		pinctrl1 = &pinctrl_z;
	};

	binman: binman {
		multiple-images;
	};

	soc {
		bootph-all;

		ddr: ddr@5a003000 {
			bootph-all;

			compatible = "st,stm32mp1-ddr";

			reg = <0x5a003000 0x550
			       0x5a004000 0x234>;

			status = "okay";
		};
	};

	/* need PSCI for sysreset during board_f */
	psci {
		bootph-some-ram;
	};
};

&bsec {
	bootph-all;
};

&gpioa {
	bootph-all;
};

&gpiob {
	bootph-all;
};

&gpioc {
	bootph-all;
};

&gpiod {
	bootph-all;
};

&gpioe {
	bootph-all;
};

&gpiof {
	bootph-all;
};

&gpiog {
	bootph-all;
};

&gpioh {
	bootph-all;
};

&gpioi {
	bootph-all;
};

&gpioj {
	bootph-all;
};

&gpiok {
	bootph-all;
};

&gpioz {
	bootph-all;
};

&optee {
	bootph-some-ram;
};

&iwdg2 {
	bootph-all;
};

/* pre-reloc probe = reserve video frame buffer in video_reserve() */
&ltdc {
	bootph-some-ram;
};

/* temp = waiting kernel update */
&m4_rproc {
	resets = <&scmi_reset RST_SCMI_MCU>,
		 <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
	reset-names = "mcu_rst", "hold_boot";
};

&pinctrl {
	bootph-all;
};

&pinctrl_z {
	bootph-all;
};

&rcc {
	bootph-all;
};

&scmi {
	bootph-some-ram;
};

&usart1 {
	resets = <&scmi_reset RST_SCMI_USART1>;
};

&usart2 {
	resets = <&rcc USART2_R>;
};

&usart3 {
	resets = <&rcc USART3_R>;
};

&uart4 {
	resets = <&rcc UART4_R>;
};

&uart5 {
	resets = <&rcc UART5_R>;
};

&usart6 {
	resets = <&rcc USART6_R>;
};

&uart7 {
	resets = <&rcc UART7_R>;
};

&uart8{
	resets = <&rcc UART8_R>;
};