| // SPDX-License-Identifier: GPL-2.0 |
| * Copyright (C) 2018 Xilinx, Inc. |
| * Michal Simek <michal.simek@amd.com> |
| #include "zynq-7000.dtsi" |
| model = "Zynq DLC20 Rev1.0"; |
| compatible = "xlnx,zynq-dlc20-rev1.0", "xlnx,zynq-dlc20", |
| stdout-path = "serial0:115200n8"; |
| usb_phy0: phy0@e0002000 { |
| reg = <0xe0002000 0x1000>; |
| ps-clk-frequency = <33333333>; /* U7 */ |
| status = "okay"; /* MIO16-MIO27, MDIO MIO52/53 */ |
| phy-handle = <ðernet_phy>; |
| ethernet_phy: ethernet-phy@7 { /* rtl8211e - U25 */ |
| status = "okay"; /* MIO14/15 */ |
| clock-frequency = <400000>; |
| compatible = "atmel,24c08"; |
| /* Rev1.0 W25Q128FWSIG, RevC N25Q128A */ |
| compatible = "n25q128a11", "jedec,spi-nor"; |
| spi-max-frequency = <50000000>; |
| status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */ |
| status = "okay"; /* MIO8/9 */ |
| status = "okay"; /* MIO28-MIO39 */ |