clk: zynq: Add dummy clock enable function
A lot of Xilinx drivers are checking -ENOSYS which means that clock driver
doesn't have enable function. Remove this checking from drivers and create
dummy enable function as was done for clk_fixed_rate driver by
commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function").
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
diff --git a/drivers/clk/clk_zynq.c b/drivers/clk/clk_zynq.c
index bf32d83..1f71b7d 100644
--- a/drivers/clk/clk_zynq.c
+++ b/drivers/clk/clk_zynq.c
@@ -444,11 +444,21 @@
}
#endif
+static int dummy_enable(struct clk *clk)
+{
+ /*
+ * Add implementation but by default all clocks are enabled
+ * after power up which is only one supported case now.
+ */
+ return 0;
+}
+
static struct clk_ops zynq_clk_ops = {
.get_rate = zynq_clk_get_rate,
#ifndef CONFIG_SPL_BUILD
.set_rate = zynq_clk_set_rate,
#endif
+ .enable = dummy_enable,
};
static int zynq_clk_probe(struct udevice *dev)