arch/arm/dts/tegra114.dtsi

#include "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra114";

	tegra_car: clock {
		compatible = "nvidia,tegra114-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra114-apbdma", "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1400>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04
			      0 128 0x04
			      0 129 0x04
			      0 130 0x04
			      0 131 0x04
			      0 132 0x04
			      0 133 0x04
			      0 134 0x04
			      0 135 0x04
			      0 136 0x04
			      0 137 0x04
			      0 138 0x04
			      0 139 0x04
			      0 140 0x04
			      0 141 0x04
			      0 142 0x04
			      0 143 0x04>;
	};

	gpio: gpio {
		compatible = "nvidia,tegra114-gpio", "nvidia,tegra30-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04
			      0 125 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>;
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>;
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>;
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000c700 0x100>;
		interrupts = <0 120 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 103>;
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra114-i2c";
		reg = <0x7000d000 0x100>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>;
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000d400 0x200>;
		interrupts = <0 59 0x04>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		/* PERIPH_ID_SBC1, PLLP_OUT0 */
		clocks = <&tegra_car 41>;
	};

	spi@7000d600 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000d600 0x200>;
		interrupts = <0 82 0x04>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		/* PERIPH_ID_SBC2, PLLP_OUT0 */
		clocks = <&tegra_car 44>;
	};

	spi@7000d800 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000d480 0x200>;
		interrupts = <0 83 0x04>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		/* PERIPH_ID_SBC3, PLLP_OUT0 */
		clocks = <&tegra_car 46>;
	};

	spi@7000da00 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000da00 0x200>;
		interrupts = <0 93 0x04>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		/* PERIPH_ID_SBC4, PLLP_OUT0 */
		clocks = <&tegra_car 68>;
	};

	spi@7000dc00 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000dc00 0x200>;
		interrupts = <0 94 0x04>;
		nvidia,dma-request-selector = <&apbdma 27>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		/* PERIPH_ID_SBC5, PLLP_OUT0 */
		clocks = <&tegra_car 104>;
	};

	spi@7000de00 {
		compatible = "nvidia,tegra114-spi";
		reg = <0x7000de00 0x200>;
		interrupts = <0 79 0x04>;
		nvidia,dma-request-selector = <&apbdma 28>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
		/* PERIPH_ID_SBC6, PLLP_OUT0 */
		clocks = <&tegra_car 105>;
	};
};