dts/upstream/src/arm64/renesas/r9a08g045.dtsi - filogic/uboot - Gitiles

 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 /*
  * Device Tree Source for the RZ/G3S SoC
  *
  * Copyright (C) 2023 Renesas Electronics Corp.
  */

 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/clock/r9a08g045-cpg.h>

 / {
 	compatible = "renesas,r9a08g045";
 	#address-cells = <2>;
 	#size-cells = <2>;

 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;

 		cpu0: cpu@0 {
 			compatible = "arm,cortex-a55";
 			reg = <0>;
 			device_type = "cpu";
 			#cooling-cells = <2>;
 			next-level-cache = <&L3_CA55>;
 			enable-method = "psci";
 			clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
 		};

 		L3_CA55: cache-controller-0 {
 			compatible = "cache";
 			cache-level = <3>;
 			cache-unified;
 			cache-size = <0x40000>;
 		};
 	};

 	extal_clk: extal-clk {
 		compatible = "fixed-clock";
 		#clock-cells = <0>;
 		/* This value must be overridden by the board. */
 		clock-frequency = <0>;
 	};

 	soc: soc {
 		compatible = "simple-bus";
 		interrupt-parent = <&gic>;
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;

 		scif0: serial@1004b800 {
 			compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
 			reg = <0 0x1004b800 0 0x400>;
 			interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "eri", "rxi", "txi",
 					  "bri", "dri", "tei";
 			clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
 			clock-names = "fck";
 			power-domains = <&cpg>;
 			resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
 			status = "disabled";
 		};

 		cpg: clock-controller@11010000 {
 			compatible = "renesas,r9a08g045-cpg";
 			reg = <0 0x11010000 0 0x10000>;
 			clocks = <&extal_clk>;
 			clock-names = "extal";
 			#clock-cells = <2>;
 			#reset-cells = <1>;
 			#power-domain-cells = <0>;
 		};

 		sysc: system-controller@11020000 {
 			compatible = "renesas,r9a08g045-sysc";
 			reg = <0 0x11020000 0 0x10000>;
 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "lpm_int", "ca55stbydone_int",
 					  "cm33stbyr_int", "ca55_deny";
 			status = "disabled";
 		};

 		pinctrl: pinctrl@11030000 {
 			compatible = "renesas,r9a08g045-pinctrl";
 			reg = <0 0x11030000 0 0x10000>;
 			gpio-controller;
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
 			interrupt-parent = <&irqc>;
 			gpio-ranges = <&pinctrl 0 0 152>;
 			clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
 			power-domains = <&cpg>;
 			resets = <&cpg R9A08G045_GPIO_RSTN>,
 				 <&cpg R9A08G045_GPIO_PORT_RESETN>,
 				 <&cpg R9A08G045_GPIO_SPARE_RESETN>;
 		};

 		irqc: interrupt-controller@11050000 {
 			compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
 			#interrupt-cells = <2>;
 			#address-cells = <0>;
 			interrupt-controller;
 			reg = <0 0x11050000 0 0x10000>;
 			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "nmi",
 					  "irq0", "irq1", "irq2", "irq3",
 					  "irq4", "irq5", "irq6", "irq7",
 					  "tint0", "tint1", "tint2", "tint3",
 					  "tint4", "tint5", "tint6", "tint7",
 					  "tint8", "tint9", "tint10", "tint11",
 					  "tint12", "tint13", "tint14", "tint15",
 					  "tint16", "tint17", "tint18", "tint19",
 					  "tint20", "tint21", "tint22", "tint23",
 					  "tint24", "tint25", "tint26", "tint27",
 					  "tint28", "tint29", "tint30", "tint31",
 					  "bus-err";
 			clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
 				 <&cpg CPG_MOD R9A08G045_IA55_PCLK>;
 			clock-names = "clk", "pclk";
 			power-domains = <&cpg>;
 			resets = <&cpg R9A08G045_IA55_RESETN>;
 		};

 		sdhi0: mmc@11c00000  {
 			compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
 			reg = <0x0 0x11c00000 0 0x10000>;
 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
 				 <&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
 				 <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
 				 <&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A08G045_SDHI0_IXRST>;
 			power-domains = <&cpg>;
 			status = "disabled";
 		};

 		sdhi1: mmc@11c10000 {
 			compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
 			reg = <0x0 0x11c10000 0 0x10000>;
 			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
 				 <&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
 				 <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
 				 <&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A08G045_SDHI1_IXRST>;
 			power-domains = <&cpg>;
 			status = "disabled";
 		};

 		sdhi2: mmc@11c20000 {
 			compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
 			reg = <0x0 0x11c20000 0 0x10000>;
 			interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
 				 <&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
 				 <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
 				 <&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
 			clock-names = "core", "clkh", "cd", "aclk";
 			resets = <&cpg R9A08G045_SDHI2_IXRST>;
 			power-domains = <&cpg>;
 			status = "disabled";
 		};

 		eth0: ethernet@11c30000 {
 			compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
 			reg = <0 0x11c30000 0 0x10000>;
 			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mux", "fil", "arp_ns";
 			phy-mode = "rgmii";
 			clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
 				 <&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
 				 <&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
 			clock-names = "axi", "chi", "refclk";
 			resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
 			power-domains = <&cpg>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 		};

 		eth1: ethernet@11c40000 {
 			compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
 			reg = <0 0x11c40000 0 0x10000>;
 			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
 				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 			interrupt-names = "mux", "fil", "arp_ns";
 			phy-mode = "rgmii";
 			clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
 				 <&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
 				 <&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
 			clock-names = "axi", "chi", "refclk";
 			resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
 			power-domains = <&cpg>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
 		};

 		gic: interrupt-controller@12400000 {
 			compatible = "arm,gic-v3";
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
 			interrupt-controller;
 			reg = <0x0 0x12400000 0 0x40000>,
 			      <0x0 0x12440000 0 0x60000>;
 			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 		};
 	};

 	timer {
 		compatible = "arm,armv8-timer";
 		interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
 				      <&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
 				      <&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
 				      <&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
 	};
 };
	// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
	/*
	* Device Tree Source for the RZ/G3S SoC
	*
	* Copyright (C) 2023 Renesas Electronics Corp.
	*/

	#include <dt-bindings/interrupt-controller/arm-gic.h>
	#include <dt-bindings/clock/r9a08g045-cpg.h>

	/ {
	compatible = "renesas,r9a08g045";
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
	#address-cells = <1>;
	#size-cells = <0>;

	cpu0: cpu@0 {
	compatible = "arm,cortex-a55";
	reg = <0>;
	device_type = "cpu";
	#cooling-cells = <2>;
	next-level-cache = <&L3_CA55>;
	enable-method = "psci";
	clocks = <&cpg CPG_CORE R9A08G045_CLK_I>;
	};

	L3_CA55: cache-controller-0 {
	compatible = "cache";
	cache-level = <3>;
	cache-unified;
	cache-size = <0x40000>;
	};
	};

	extal_clk: extal-clk {
	compatible = "fixed-clock";
	#clock-cells = <0>;
	/* This value must be overridden by the board. */
	clock-frequency = <0>;
	};

	soc: soc {
	compatible = "simple-bus";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	scif0: serial@1004b800 {
	compatible = "renesas,scif-r9a08g045", "renesas,scif-r9a07g044";
	reg = <0 0x1004b800 0 0x400>;
	interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "eri", "rxi", "txi",
	"bri", "dri", "tei";
	clocks = <&cpg CPG_MOD R9A08G045_SCIF0_CLK_PCK>;
	clock-names = "fck";
	power-domains = <&cpg>;
	resets = <&cpg R9A08G045_SCIF0_RST_SYSTEM_N>;
	status = "disabled";
	};

	cpg: clock-controller@11010000 {
	compatible = "renesas,r9a08g045-cpg";
	reg = <0 0x11010000 0 0x10000>;
	clocks = <&extal_clk>;
	clock-names = "extal";
	#clock-cells = <2>;
	#reset-cells = <1>;
	#power-domain-cells = <0>;
	};

	sysc: system-controller@11020000 {
	compatible = "renesas,r9a08g045-sysc";
	reg = <0 0x11020000 0 0x10000>;
	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "lpm_int", "ca55stbydone_int",
	"cm33stbyr_int", "ca55_deny";
	status = "disabled";
	};

	pinctrl: pinctrl@11030000 {
	compatible = "renesas,r9a08g045-pinctrl";
	reg = <0 0x11030000 0 0x10000>;
	gpio-controller;
	#gpio-cells = <2>;
	interrupt-controller;
	#interrupt-cells = <2>;
	interrupt-parent = <&irqc>;
	gpio-ranges = <&pinctrl 0 0 152>;
	clocks = <&cpg CPG_MOD R9A08G045_GPIO_HCLK>;
	power-domains = <&cpg>;
	resets = <&cpg R9A08G045_GPIO_RSTN>,
	<&cpg R9A08G045_GPIO_PORT_RESETN>,
	<&cpg R9A08G045_GPIO_SPARE_RESETN>;
	};

	irqc: interrupt-controller@11050000 {
	compatible = "renesas,r9a08g045-irqc", "renesas,rzg2l-irqc";
	#interrupt-cells = <2>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0 0x11050000 0 0x10000>;
	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "nmi",
	"irq0", "irq1", "irq2", "irq3",
	"irq4", "irq5", "irq6", "irq7",
	"tint0", "tint1", "tint2", "tint3",
	"tint4", "tint5", "tint6", "tint7",
	"tint8", "tint9", "tint10", "tint11",
	"tint12", "tint13", "tint14", "tint15",
	"tint16", "tint17", "tint18", "tint19",
	"tint20", "tint21", "tint22", "tint23",
	"tint24", "tint25", "tint26", "tint27",
	"tint28", "tint29", "tint30", "tint31",
	"bus-err";
	clocks = <&cpg CPG_MOD R9A08G045_IA55_CLK>,
	<&cpg CPG_MOD R9A08G045_IA55_PCLK>;
	clock-names = "clk", "pclk";
	power-domains = <&cpg>;
	resets = <&cpg R9A08G045_IA55_RESETN>;
	};

	sdhi0: mmc@11c00000 {
	compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
	reg = <0x0 0x11c00000 0 0x10000>;
	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD R9A08G045_SDHI0_IMCLK>,
	<&cpg CPG_MOD R9A08G045_SDHI0_CLK_HS>,
	<&cpg CPG_MOD R9A08G045_SDHI0_IMCLK2>,
	<&cpg CPG_MOD R9A08G045_SDHI0_ACLK>;
	clock-names = "core", "clkh", "cd", "aclk";
	resets = <&cpg R9A08G045_SDHI0_IXRST>;
	power-domains = <&cpg>;
	status = "disabled";
	};

	sdhi1: mmc@11c10000 {
	compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
	reg = <0x0 0x11c10000 0 0x10000>;
	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD R9A08G045_SDHI1_IMCLK>,
	<&cpg CPG_MOD R9A08G045_SDHI1_CLK_HS>,
	<&cpg CPG_MOD R9A08G045_SDHI1_IMCLK2>,
	<&cpg CPG_MOD R9A08G045_SDHI1_ACLK>;
	clock-names = "core", "clkh", "cd", "aclk";
	resets = <&cpg R9A08G045_SDHI1_IXRST>;
	power-domains = <&cpg>;
	status = "disabled";
	};

	sdhi2: mmc@11c20000 {
	compatible = "renesas,sdhi-r9a08g045", "renesas,rcar-gen3-sdhi";
	reg = <0x0 0x11c20000 0 0x10000>;
	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
	clocks = <&cpg CPG_MOD R9A08G045_SDHI2_IMCLK>,
	<&cpg CPG_MOD R9A08G045_SDHI2_CLK_HS>,
	<&cpg CPG_MOD R9A08G045_SDHI2_IMCLK2>,
	<&cpg CPG_MOD R9A08G045_SDHI2_ACLK>;
	clock-names = "core", "clkh", "cd", "aclk";
	resets = <&cpg R9A08G045_SDHI2_IXRST>;
	power-domains = <&cpg>;
	status = "disabled";
	};

	eth0: ethernet@11c30000 {
	compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
	reg = <0 0x11c30000 0 0x10000>;
	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mux", "fil", "arp_ns";
	phy-mode = "rgmii";
	clocks = <&cpg CPG_MOD R9A08G045_ETH0_CLK_AXI>,
	<&cpg CPG_MOD R9A08G045_ETH0_CLK_CHI>,
	<&cpg CPG_MOD R9A08G045_ETH0_REFCLK>;
	clock-names = "axi", "chi", "refclk";
	resets = <&cpg R9A08G045_ETH0_RST_HW_N>;
	power-domains = <&cpg>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	eth1: ethernet@11c40000 {
	compatible = "renesas,r9a08g045-gbeth", "renesas,rzg2l-gbeth";
	reg = <0 0x11c40000 0 0x10000>;
	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
	<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "mux", "fil", "arp_ns";
	phy-mode = "rgmii";
	clocks = <&cpg CPG_MOD R9A08G045_ETH1_CLK_AXI>,
	<&cpg CPG_MOD R9A08G045_ETH1_CLK_CHI>,
	<&cpg CPG_MOD R9A08G045_ETH1_REFCLK>;
	clock-names = "axi", "chi", "refclk";
	resets = <&cpg R9A08G045_ETH1_RST_HW_N>;
	power-domains = <&cpg>;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "disabled";
	};

	gic: interrupt-controller@12400000 {
	compatible = "arm,gic-v3";
	#interrupt-cells = <3>;
	#address-cells = <0>;
	interrupt-controller;
	reg = <0x0 0x12400000 0 0x40000>,
	<0x0 0x12440000 0 0x60000>;
	interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
	};
	};

	timer {
	compatible = "arm,armv8-timer";
	interrupts-extended = <&gic GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
	<&gic GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
	<&gic GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
	<&gic GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
	};
	};