clk: rockchip: rk3568: Include UART clocks in SPL
The clock driver for RK3568 does not include support for UART clocks in
SPL. This result in the following message with high enough loglevel.
ns16550_serial serial@fe660000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19
Fix this by including support for UART clocks in SPL.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c
index dab254d..dabc7e7 100644
--- a/drivers/clk/rockchip/clk_rk3568.c
+++ b/drivers/clk/rockchip/clk_rk3568.c
@@ -2189,6 +2189,7 @@
return rk3568_rkvdec_get_clk(priv, clk_id);
}
+#endif
static ulong rk3568_uart_get_rate(struct rk3568_clk_priv *priv, ulong clk_id)
{
@@ -2324,7 +2325,6 @@
return rk3568_uart_get_rate(priv, clk_id);
}
-#endif
static ulong rk3568_clk_get_rate(struct clk *clk)
{
@@ -2463,6 +2463,7 @@
case TCLK_WDT_NS:
rate = OSC_HZ;
break;
+#endif
case SCLK_UART1:
case SCLK_UART2:
case SCLK_UART3:
@@ -2474,7 +2475,6 @@
case SCLK_UART9:
rate = rk3568_uart_get_rate(priv, clk->id);
break;
-#endif
case ACLK_SECURE_FLASH:
case ACLK_CRYPTO_NS:
case HCLK_SECURE_FLASH:
@@ -2648,6 +2648,7 @@
case TCLK_WDT_NS:
ret = OSC_HZ;
break;
+#endif
case SCLK_UART1:
case SCLK_UART2:
case SCLK_UART3:
@@ -2659,7 +2660,6 @@
case SCLK_UART9:
ret = rk3568_uart_set_rate(priv, clk->id, rate);
break;
-#endif
case ACLK_SECURE_FLASH:
case ACLK_CRYPTO_NS:
case HCLK_SECURE_FLASH: