| commit | f51ca5cc26d3a7cddee5f6cea8f303d257e45094 | [log] [tgz] |
|---|---|---|
| author | Jonas Karlman <jonas@kwiboo.se> | Fri Aug 04 09:33:59 2023 +0000 |
| committer | Kever Yang <kever.yang@rock-chips.com> | Sat Aug 12 10:35:35 2023 +0800 |
| tree | 9d3c048a08ce7d74434eedc808996281387cc564 | |
| parent | 46e99933b6875bf85b11c5c239fd8f061cf91006 [diff] |
clk: rockchip: rk3568: Fix mask for clk_cpll_div_25m_div
The field for clk_cpll_div_25m_div in CRU_CLKSEL_CON81 is 6 bits wide,
not 5 bits wide as currently defined in CPLL_25M_DIV_MASK.
Fix this and the assert so that CPLL_25M can be assigned a 25 MHz rate.
Fixes: 4a262feba3a5 ("rockchip: rk3568: add clock driver")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>