global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index ff73596..ed89011 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -84,7 +84,7 @@
static void check_erratum_a4580(uint32_t svr)
{
const serdes_corenet_t __iomem *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
unsigned int lane;
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 432d4b1..49a1aac 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -98,7 +98,7 @@
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
if (SVR_SOC_VER(svr) == SVR_T4080) {
ccsr_rcpm_t *rcpm =
- (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ (void __iomem *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
FSL_CORENET_DEVDISR2_DTSEC1_9);
@@ -540,16 +540,16 @@
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
switch (i) {
case 0:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 9fb7802..47bea51 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -160,7 +160,7 @@
{
int i;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
@@ -217,7 +217,7 @@
char cpc_subarg[16];
bool have_hwconfig = false;
int cpc_args = 0;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
/* Extract hwconfig from environment */
ret = env_get_f("hwconfig", buffer, sizeof(buffer));
@@ -271,7 +271,7 @@
static void invalidate_cpc(void)
{
int i;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
/* skip CPC when it used as all SRAM */
@@ -300,7 +300,7 @@
static void corenet_tb_init(void)
{
volatile ccsr_rcpm_t *rcpm =
- (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
volatile ccsr_pic_t *pic =
(void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
u32 whoami = in_be32(&pic->whoami);
@@ -476,7 +476,7 @@
do {
int j, cluster_valid = 0;
- l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+ l2cache = (void __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
cluster = in_be32(&gur->tp_cluster[i].lower);
@@ -518,7 +518,7 @@
#ifdef CONFIG_L2_CACHE
ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
- struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
+ struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2;
#endif
puts ("L2: ");
@@ -664,7 +664,7 @@
const char *spin;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
- ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 811e6d6..1161938 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -164,7 +164,7 @@
static inline void ft_fixup_l3cache(void *blob, int off)
{
u32 line_size, num_ways, size, num_sets;
- cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR;
u32 cfg0 = in_be32(&cpc->cpccfg0);
size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
@@ -299,7 +299,7 @@
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
#else
struct ccsr_cluster_l2 *l2cache =
- (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
+ (struct ccsr_cluster_l2 __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2);
u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
#endif
u32 size, line_size, num_ways, num_sets;
@@ -466,11 +466,11 @@
get_sys_info(&sysinfo);
#ifdef CONFIG_SYS_DPAA_FMAN
- ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
+ ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET,
sysinfo.freq_fman[0]);
#if (CONFIG_SYS_NUM_FMAN == 2)
- ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
+ ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET,
sysinfo.freq_fman[1]);
#endif
#endif
@@ -611,7 +611,7 @@
else {
ccsr_sec_t __iomem *sec;
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 1a30395..3a6ce32 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -21,10 +21,10 @@
#ifdef CONFIG_SYS_FSL_SRDS_2
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
#endif
@@ -104,13 +104,13 @@
ret |= serdes2_prtcl_map[device];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
if (!serdes3_prtcl_map[NONE])
fsl_serdes_init();
ret |= serdes3_prtcl_map[device];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
if (!serdes4_prtcl_map[NONE])
fsl_serdes_init();
@@ -139,13 +139,13 @@
cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
break;
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
case FSL_SRDS_3:
cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
break;
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
case FSL_SRDS_4:
cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
@@ -351,28 +351,28 @@
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
serdes_init(FSL_SRDS_3,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
serdes3_prtcl_map);
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
serdes_init(FSL_SRDS_4,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
serdes4_prtcl_map);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 1d35733..437ecde 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -109,7 +109,7 @@
int serdes_lane_enabled(int lane)
{
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
int bank = lanes[lane].bank;
int word = lanes[lane].lpd / 32;
@@ -257,7 +257,7 @@
if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
return;
- regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ regs = (typeof(regs))CFG_SYS_FSL_CORENET_SERDES_ADDR;
prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
__serdes_reset_rx(regs, prtcl, device);
@@ -466,7 +466,7 @@
static void wait_for_rstdone(unsigned int bank)
{
serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
unsigned long long end_tick;
u32 rstctl;
@@ -527,7 +527,7 @@
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
return;
- srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
@@ -601,7 +601,7 @@
serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
break;
default:
- srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+ srds2_regs = (void *)CFG_SYS_FSL_CORENET_SERDES2_ADDR;
/* We don't need bank 4, so power it down */
setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 34974c9..9ad48d4 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -76,7 +76,7 @@
static void setup_sec_liodn_base(void)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
u32 base;
if (!IS_E_PROCESSOR(get_svr()))
@@ -101,12 +101,12 @@
switch(dev) {
case FSL_HW_PORTAL_FMAN1:
- fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+ fm = (void *)CFG_SYS_FSL_FM1_ADDR;
break;
#if (CONFIG_SYS_NUM_FMAN == 2)
case FSL_HW_PORTAL_FMAN2:
- fm = (void *)CONFIG_SYS_FSL_FM2_ADDR;
+ fm = (void *)CFG_SYS_FSL_FM2_ADDR;
break;
#endif
default:
@@ -130,7 +130,7 @@
static void setup_pme_liodn_base(void)
{
#ifdef CONFIG_SYS_DPAA_PME
- ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+ ccsr_pme_t *pme = (void *)CFG_SYS_FSL_CORENET_PME_ADDR;
u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) |
liodn_bases[FSL_HW_PORTAL_PME].id[1];
@@ -141,7 +141,7 @@
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
static void setup_raide_liodn_base(void)
{
- struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR;
+ struct ccsr_raide *raide = (void *)CFG_SYS_FSL_RAID_ENGINE_ADDR;
/* setup raid engine liodn base for data/desc ; both set to 47 */
u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) |
@@ -155,7 +155,7 @@
static void set_rman_liodn(struct liodn_id_table *tbl, int size)
{
int i;
- struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
+ struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
for (i = 0; i < size; i++) {
/* write the RMan block number */
@@ -168,7 +168,7 @@
static void setup_rman_liodn_base(struct liodn_id_table *tbl, int size)
{
int i;
- struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
+ struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
u32 base = liodn_bases[FSL_HW_PORTAL_RMAN].id[0];
out_be32(&rman->mmliodnbr, base);
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index e1469eb..f109ecb 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -265,8 +265,8 @@
struct law_entry e;
gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
- rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR);
+ rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
whoami = in_be32(&pic->whoami);
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index a7004a6..31d0481 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -26,14 +26,14 @@
{
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
- volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+ volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
#ifdef CONFIG_HETROGENOUS_CLUSTERS
unsigned int dsp_cpu;
uint rcw_tmp1, rcw_tmp2;
#endif
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
- int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+ int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
#endif
__maybe_unused u32 svr;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 024414e..5341756 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -966,7 +966,7 @@
erratum_set_dcsr 0xb0e38 0xe0400000
erratum_set_dcsr 0xb0008 0x00900000
erratum_set_dcsr 0xb0e40 0xe00a0000
- erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+ erratum_set_ccsr 0x18600 CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
#ifdef CONFIG_RAMBOOT_PBL
erratum_set_ccsr 0x10f00 0x495e5000
#else
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 4e3f900..dd27416 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -20,7 +20,7 @@
#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
#ifdef CONFIG_FSL_CORENET
-#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
+#define LAW_BASE (CFG_SYS_FSL_CORENET_CCM_ADDR)
#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 62524a2..c815d19 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -79,9 +79,9 @@
int idx, first, last;
u32 i;
unsigned long long end_tick;
- struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio_regs = (void *)CFG_SYS_FSL_SRIO_ADDR;
- srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
>> (12 - port * 4)) & 0x3;
init_lane = (in_be32((void *)&srio_regs->lp_serial
@@ -291,7 +291,7 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
- struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
out_be32((void *)&srio->impl.port[port - 1].ptaacr,
@@ -343,7 +343,7 @@
void srio_boot_master_release_slave(int port)
{
- struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
u32 escsr;
debug("SRIOBOOT - MASTER: "
"Check the port status and release slave core ...\n");