global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c
index 86b5b21..4e1fe28 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -15,8 +15,8 @@
void get_sys_info(struct sys_info *sys_info)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[6] = {
[0] = 0, /* CC1 PPL / 1 */
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 0b3e3b2..d530e06 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -228,7 +228,7 @@
uint get_svr(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return in_be32(&gur->svr);
}
@@ -237,7 +237,7 @@
int print_cpuinfo(void)
{
char buf1[32], buf2[32];
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major, minor, ver, i;
svr = in_be32(&gur->svr);
@@ -316,7 +316,7 @@
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
- struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
u32 state;
icache_enable();
@@ -355,7 +355,7 @@
/* Set the address at which the secondary core starts from.*/
void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->scratchrw[0], addr);
}
@@ -363,7 +363,7 @@
/* Release the secondary core from holdoff state and kick it */
void smp_kick_all_cpus(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->brrl, 0x2);
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 83f9882..c01cebb 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -92,7 +92,7 @@
int off;
int val;
const char *sysclk_path;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr;
svr = in_be32(&gur->svr);
@@ -105,7 +105,7 @@
else {
ccsr_sec_t __iomem *sec;
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
index caf51e1..f74d819 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
@@ -39,7 +39,7 @@
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = in_be32(&gur->rcwsr[4]);
int i;
@@ -74,7 +74,7 @@
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
@@ -103,14 +103,14 @@
#ifdef CONFIG_SYS_FSL_SRDS_1
if (!(serdes1_prtcl_map & (1ULL << NONE)))
serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_SERDES_ADDR,
+ CFG_SYS_FSL_SERDES_ADDR,
RCWSR4_SRDS1_PRTCL_MASK,
RCWSR4_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
if (!(serdes2_prtcl_map & (1ULL << NONE)))
serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_SERDES_ADDR +
+ CFG_SYS_FSL_SERDES_ADDR +
FSL_SRDS_2 * 0x1000,
RCWSR4_SRDS2_PRTCL_MASK,
RCWSR4_SRDS2_PRTCL_SHIFT);
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index 28a7945..b4d113d 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -31,7 +31,7 @@
{
const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
out_le32(&scfg->sparecr[2], dest);
@@ -57,8 +57,8 @@
static void __secure ls1_deepsleep_irq_cfg(void)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
/* Mask interrupts from GIC */
@@ -120,8 +120,8 @@
{
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Set HRSTCR */
setbits_be32(&scfg->hrstcr, 0x80000000);
@@ -155,9 +155,9 @@
static void __secure ls1_deep_sleep(u32 entry_point)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;
void *qixis_base = (void *)QIXIS_BASE;
@@ -213,8 +213,8 @@
#else
static void __secure ls1_sleep(void)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index 3956178..e7c4fbf 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -129,8 +129,8 @@
mov r1, r4
@ Get DCFG base address
- movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+ movw r4, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+ movt r4, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
@ Detect target CPU state
ldr r2, [r4, #DCFG_CCSR_BRR]
@@ -141,8 +141,8 @@
@ Reset target CPU
@ Get SCFG base address
- movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
- movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
+ movw r0, #(CFG_SYS_FSL_SCFG_ADDR & 0xffff)
+ movt r0, #(CFG_SYS_FSL_SCFG_ADDR >> 16)
@ Enable CORE Soft Reset
movw r5, #0
@@ -216,8 +216,8 @@
mov r1, r4
@ Get RCPM base address
- movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+ movw r4, #(CFG_SYS_FSL_RCPM_ADDR & 0xffff)
+ movt r4, #(CFG_SYS_FSL_RCPM_ADDR >> 16)
mov r0, #PSCI_AFFINITY_LEVEL_ON
@@ -236,8 +236,8 @@
.globl psci_system_reset
psci_system_reset:
@ Get DCFG base address
- movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+ movw r1, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+ movt r1, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
rev r2, r2
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 728efc4..1dafa3c 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -54,7 +54,7 @@
unsigned int get_soc_major_rev(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major;
svr = in_be32(&gur->svr);
@@ -113,7 +113,7 @@
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* disables propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
@@ -129,7 +129,7 @@
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
/* enable propagation of barrier transactions to DDRC from CCI400 */
@@ -161,7 +161,7 @@
int arch_soc_init(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 487c0ed..c11341a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -96,11 +96,11 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE},
#ifdef CONFIG_FSL_IFC
@@ -159,7 +159,7 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@@ -168,7 +168,7 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
},
@@ -204,7 +204,7 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@@ -213,12 +213,12 @@
PTE_BLOCK_MEMTYPE(MT_NORMAL) |
PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS
},
- { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+ { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1,
CONFIG_SYS_FSL_QSPI_SIZE1,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
+ { CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2,
CONFIG_SYS_FSL_QSPI_SIZE2,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -333,7 +333,7 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+ { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE,
SYS_FSL_OCRAM_SPACE_SIZE,
PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
},
@@ -342,7 +342,7 @@
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
- { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+ { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE,
CONFIG_SYS_FSL_QSPI_SIZE,
PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
@@ -401,7 +401,7 @@
void cpu_name(char *name)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int i, svr, ver;
svr = gur_in32(&gur->svr);
@@ -430,7 +430,7 @@
#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
/*
* To start MMU before DDR is available, we create MMU table in SRAM.
- * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three
+ * The base address of SRAM is CFG_SYS_FSL_OCRAM_BASE. We use three
* levels of translation tables here to cover 40-bit address space.
* We use 4KB granule size, with 40 bits physical address, T0SZ=24
* Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose.
@@ -443,7 +443,7 @@
/* global data is already setup, no allocation yet */
if (el == 3)
- gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+ gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE;
else
gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
gd->arch.tlb_fillptr = gd->arch.tlb_addr;
@@ -466,7 +466,7 @@
#ifdef CONFIG_ARCH_LS2080A
unsigned int i;
u32 svr, ver;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
svr = gur_in32(&gur->svr);
ver = SVR_SOC_VER(svr);
@@ -775,7 +775,7 @@
#if defined(CONFIG_FSL_LSCH3)
u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
#elif defined(CONFIG_FSL_LSCH2)
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#endif
if (current_el() == 2) {
@@ -863,7 +863,7 @@
u32 initiator_type(u32 cluster, int init_id)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK;
u32 type = 0;
@@ -876,7 +876,7 @@
u32 cpu_pos_mask(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0;
u32 cluster, type, mask = 0;
@@ -897,7 +897,7 @@
u32 cpu_mask(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster, type, mask = 0;
@@ -930,7 +930,7 @@
int fsl_qoriq_core_to_cluster(unsigned int core)
{
struct ccsr_gur __iomem *gur =
- (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster;
@@ -954,7 +954,7 @@
u32 fsl_qoriq_core_to_type(unsigned int core)
{
struct ccsr_gur __iomem *gur =
- (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR);
int i = 0, count = 0;
u32 cluster, type;
@@ -979,7 +979,7 @@
#ifndef CONFIG_FSL_LSCH3
uint get_svr(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return gur_in32(&gur->svr);
}
@@ -988,7 +988,7 @@
#ifdef CONFIG_DISPLAY_CPUINFO
int print_cpuinfo(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct sys_info sysinfo;
char buf[32];
unsigned int i, core;
@@ -1179,9 +1179,9 @@
int timer_init(void)
{
- u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
+ u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR;
#ifdef CONFIG_FSL_LSCH3
- u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
+ u32 __iomem *cltbenr = (u32 *)CFG_SYS_FSL_PMU_CLTBENR;
#endif
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
defined(CONFIG_ARCH_LS1028A)
@@ -1230,7 +1230,7 @@
}
#if !CONFIG_IS_ENABLED(SYSRESET)
-__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
+__efi_runtime_data u32 __iomem *rstcr = (u32 *)CFG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(void)
{
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 427de1c..ee73457 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -171,9 +171,9 @@
{
int offset, err;
u64 reg[8];
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int val;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int align_64k = 0;
val = gur_in32(&gur->svr);
@@ -355,7 +355,7 @@
static void fdt_fixup_msi(void *blob)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int rev;
rev = gur_in32(&gur->svr);
@@ -620,7 +620,7 @@
void ft_cpu_setup(void *blob, struct bd_info *bd)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr);
/* delete crypto node if not on an E-processor */
@@ -635,7 +635,7 @@
fdt_fixup_kaslr(blob);
#endif
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
index 60769e1..1541dfb 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c
@@ -40,7 +40,7 @@
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]);
int i;
@@ -76,7 +76,7 @@
int get_serdes_protocol(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = gur_in32(&gur->rcwsr[4]) &
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
@@ -101,7 +101,7 @@
void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift,
u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg;
int lane;
@@ -142,7 +142,7 @@
int setup_serdes_volt(u32 svdd)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_serdes *serdes1_base;
#ifdef CONFIG_SYS_FSL_SRDS_2
struct ccsr_serdes *serdes2_base;
@@ -168,7 +168,7 @@
if (svdd_cur == svdd_tar)
return 0;
- serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR;
+ serdes1_base = (void *)CFG_SYS_FSL_SERDES_ADDR;
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes2_base = (void *)serdes1_base + 0x10000;
#endif
@@ -406,14 +406,14 @@
{
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_SERDES_ADDR,
+ CFG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_SERDES_ADDR,
+ CFG_SYS_FSL_SERDES_ADDR,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK,
FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
index 898ed09..6440ce7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
@@ -20,7 +20,7 @@
void get_sys_info(struct sys_info *sys_info)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
/* rcw_tmp is needed to get FMAN clock, or to get cluster group A
* mux 2 clock for LS1043A/LS1046A.
*/
@@ -29,7 +29,7 @@
defined(CONFIG_ARCH_LS1043A)
u32 rcw_tmp;
#endif
- struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR);
+ struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[8] = {
[0] = 0, /* CC1 PPL / 1 */
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 181bd9c..c0efc34 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -86,7 +86,7 @@
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = 0;
int i;
@@ -134,7 +134,7 @@
void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT])
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg;
int lane;
@@ -399,18 +399,18 @@
int setup_serdes_volt(u32 svdd)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_serdes __iomem *serdes1_base =
- (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_LSCH3_SERDES_ADDR;
u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]);
#ifdef CONFIG_SYS_FSL_SRDS_2
struct ccsr_serdes __iomem *serdes2_base =
- (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
+ (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
struct ccsr_serdes __iomem *serdes3_base =
- (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
+ (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
#endif
u32 cfg_tmp;
@@ -585,7 +585,7 @@
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_LSCH3_SERDES_ADDR,
+ CFG_SYS_FSL_LSCH3_SERDES_ADDR,
FSL_CHASSIS3_SRDS1_REGSR,
FSL_CHASSIS3_SRDS1_PRTCL_MASK,
FSL_CHASSIS3_SRDS1_PRTCL_SHIFT,
@@ -593,7 +593,7 @@
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
+ CFG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000,
FSL_CHASSIS3_SRDS2_REGSR,
FSL_CHASSIS3_SRDS2_PRTCL_MASK,
FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
@@ -601,7 +601,7 @@
#endif
#ifdef CONFIG_SYS_NXP_SRDS_3
serdes_init(NXP_SRDS_3,
- CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
+ CFG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
FSL_CHASSIS3_SRDS3_REGSR,
FSL_CHASSIS3_SRDS3_PRTCL_MASK,
FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
@@ -611,7 +611,7 @@
int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
char scfg[16], snum[16];
int cfgr = 0;
u32 cfg;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index 58080d0..137778d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -23,13 +23,13 @@
void get_sys_info(struct sys_info *sys_info)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
struct ccsr_clk_cluster_group __iomem *clk_grp[2] = {
- (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR),
- (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR)
+ (void *)(CFG_SYS_FSL_CH3_CLK_GRPA_ADDR),
+ (void *)(CFG_SYS_FSL_CH3_CLK_GRPB_ADDR)
};
struct ccsr_clk_ctrl __iomem *clk_ctrl =
- (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR);
+ (void *)(CFG_SYS_FSL_CH3_CLK_CTRL_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[16] = {
[0] = 0, /* CC1 PPL / 1 */
@@ -68,7 +68,7 @@
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = get_board_sys_clk();
- int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+ int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
u32 c_pll_sel, cplx_pll;
void *offset;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index 2d87281..e972603 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -27,7 +27,7 @@
void set_fman_icids(struct fman_icid_id_table *tbl, int size)
{
int i;
- ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+ ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
for (i = 0; i < size; i++) {
out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index 87410c7..4358c6e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -325,8 +325,8 @@
ENTRY(fsl_clear_ocram)
/* Clear OCRAM */
- ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE
- ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
+ ldr x0, =CFG_SYS_FSL_OCRAM_BASE
+ ldr x1, =(CFG_SYS_FSL_OCRAM_BASE + CFG_SYS_FSL_OCRAM_SIZE)
mov x2, #0
clear_loop:
str x2, [x0]
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
index 26f8a49..fe667f0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
@@ -53,7 +53,7 @@
bool soc_has_mac1(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr = gur_in32(&gur->svr);
unsigned int version = SVR_SOC_VER(svr);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
index 7222119..ce0c46a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c
@@ -48,8 +48,8 @@
#ifdef CONFIG_FSL_LSCH3
static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
u32 mpidr = 0;
mpidr = ((cluster << 8) | core);
@@ -73,13 +73,13 @@
int fsl_layerscape_wake_seconday_cores(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
#ifdef CONFIG_FSL_LSCH3
- struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
+ struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR);
u32 svr, ver, cluster, type;
int j = 0, cluster_cores = 0;
#elif defined(CONFIG_FSL_LSCH2)
- struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+ struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
#endif
u32 cores, cpu_up_mask = 1;
int i, timeout = 10;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
index b9894d4..117b7a0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c
@@ -253,7 +253,7 @@
#endif
#ifdef CONFIG_FSL_LSCH3
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
boot_loc_ptr_l = &gur->bootlocptrl;
boot_loc_ptr_h = &gur->bootlocptrh;
@@ -261,7 +261,7 @@
loadable_l = &gur->scratchrw[4];
loadable_h = &gur->scratchrw[5];
#elif defined(CONFIG_FSL_LSCH2)
- struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
+ struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR);
boot_loc_ptr_l = &scfg->scratchrw[1];
boot_loc_ptr_h = &scfg->scratchrw[0];
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 515dbe0..89a6262 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -80,7 +80,7 @@
bool soc_has_dp_ddr(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
/* LS2085A, LS2088A, LS2048A has DP_DDR */
@@ -94,7 +94,7 @@
bool soc_has_aiop(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 svr = gur_in32(&gur->svr);
/* LS2085A has AIOP */
@@ -249,13 +249,13 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_A008336
u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR
- eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR_ADDR
+ eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002);
#endif
-#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR
- eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR
+ eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800;
if (fsl_ddr_get_version(0) == 0x50200)
out_le32(eddrtqcr1, 0x63b30002);
#endif
@@ -271,8 +271,8 @@
#ifdef CONFIG_SYS_FSL_ERRATUM_A008514
u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR
- eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
+#ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR
+ eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800;
out_le32(eddrtqcr1, 0x63b20002);
#endif
#endif
@@ -412,7 +412,7 @@
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int vdd;
u32 fusesr;
u8 vid;
@@ -462,7 +462,7 @@
static void erratum_a009660(void)
{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009660
- u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c;
+ u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c;
out_be32(eddrtqcr1, 0x63b20042);
#endif
}
@@ -473,7 +473,7 @@
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */
if (current_el() < 3)
@@ -493,7 +493,7 @@
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
/* Skip if running at lower exception level */
@@ -526,21 +526,21 @@
static void erratum_a010539(void)
{
#if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT)
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 porsr1;
porsr1 = in_be32(&gur->porsr1);
porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK;
out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1),
porsr1);
- out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
+ out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff);
#endif
}
/* Get VDD in the unit mV from voltage ID */
int get_core_volt_from_fuse(void)
{
- struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
int vdd;
u32 fusesr;
u8 vid;
@@ -588,7 +588,7 @@
#ifdef CONFIG_SYS_FSL_DDR
static void ddr_enable_0v9_volt(bool en)
{
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
tmp = ddr_in32(&ddr->ddr_cdr1);
@@ -629,7 +629,7 @@
#ifdef CONFIG_FSL_PFE
void init_pfe_scfg_dcfg_regs(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
u32 ecccr2;
out_be32(&scfg->pfeasbcr,
@@ -653,7 +653,7 @@
{
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT)
enum boot_src src;
#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 5824778..ff752c2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -24,7 +24,7 @@
#define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 }
#define SRDS_MAX_LANES 8
#define CONFIG_SYS_PAGE_SIZE 0x10000
#ifndef L1_CACHE_BYTES
@@ -32,9 +32,9 @@
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#endif
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
@@ -95,7 +95,7 @@
#define EPU_EPGCR 0x700060000ULL
#elif defined(CONFIG_ARCH_LS1088A)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4
@@ -126,9 +126,9 @@
#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* LX2160A/LX2162A Soc Support */
#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
@@ -139,13 +139,13 @@
#define L1_CACHE_SHIFT 6
#define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT)
#endif
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* DDR */
#define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30)
@@ -161,7 +161,7 @@
/* DCFG - GUR */
#elif defined(CONFIG_ARCH_LS1028A)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 }
#define CONFIG_FSL_TZASC_400
/* TZ Protection Controller Definitions */
@@ -180,9 +180,9 @@
#define SRDS_MAX_LANES 4
#define SRDS_BITS_PER_LANE 4
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* Generic Interrupt Controller Definitions */
#define GICD_BASE 0x06000000
@@ -200,9 +200,9 @@
/* DCFG - GUR */
#elif defined(CONFIG_FSL_LSCH2)
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
+#define CFG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */
#define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */
-#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
+#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
#define DCSR_DCFG_SBEESR2 0x20140534
#define DCSR_DCFG_MBEESR2 0x20140544
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index c51b65e..4db4791 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -10,7 +10,7 @@
#ifdef CONFIG_FSL_LSCH3
#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
-#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
+#define CFG_SYS_FSL_QSPI_BASE1 0x20000000
#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
@@ -19,7 +19,7 @@
#endif
#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
-#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
+#define CFG_SYS_FSL_QSPI_BASE2 0x400000000
#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
@@ -73,7 +73,7 @@
#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
-#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
+#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 8af0d35..9cddb41 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -70,7 +70,7 @@
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \
- offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
+ offsetof(struct ccsr_scfg, name) + CFG_SYS_FSL_SCFG_ADDR, \
compataddr, SCFG_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
@@ -83,7 +83,7 @@
#define SET_SDHC_ICID(streamid) \
SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\
- CONFIG_SYS_FSL_ESDHC_ADDR)
+ CFG_SYS_FSL_ESDHC_ADDR)
#define SET_EDMA_ICID(streamid) \
SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\
@@ -102,14 +102,14 @@
#define SET_QMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
offsetof(struct ccsr_qman, liodnr) + \
- CONFIG_SYS_FSL_QMAN_ADDR, \
- CONFIG_SYS_FSL_QMAN_ADDR, false)
+ CFG_SYS_FSL_QMAN_ADDR, \
+ CFG_SYS_FSL_QMAN_ADDR, false)
#define SET_BMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,bman", streamid, streamid, \
offsetof(struct ccsr_bman, liodnr) + \
- CONFIG_SYS_FSL_BMAN_ADDR, \
- CONFIG_SYS_FSL_BMAN_ADDR, false)
+ CFG_SYS_FSL_BMAN_ADDR, \
+ CFG_SYS_FSL_BMAN_ADDR, false)
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \
{ .port_id = (_port_id), .icid = (streamid) }
@@ -119,8 +119,8 @@
#define SET_SEC_QI_ICID(streamid) \
SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \
0, offsetof(ccsr_sec_t, qilcr_ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, \
- CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
+ CFG_SYS_FSL_SEC_ADDR, \
+ CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
extern struct fman_icid_id_table fman_icid_tbl[];
extern int fman_icid_tbl_sz;
@@ -137,7 +137,7 @@
#define SET_GUR_ICID(compat, streamid, name, compataddr) \
SET_ICID_ENTRY(compat, streamid, streamid, \
- offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \
+ offsetof(struct ccsr_gur, name) + CFG_SYS_FSL_GUTS_ADDR, \
compataddr, GUR_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \
@@ -180,24 +180,24 @@
SET_ICID_ENTRY( \
(CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \
(FSL_SEC_JR##jr_num##_OFFSET == \
- SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \
+ SEC_JR3_OFFSET + CFG_SYS_FSL_SEC_OFFSET) \
? NULL \
: "fsl,sec-v4.0-job-ring"), \
streamid, \
SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, \
+ CFG_SYS_FSL_SEC_ADDR, \
FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+ CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \
SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \
offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \
- CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
+ CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
extern struct icid_id_table icid_tbl[];
extern int icid_tbl_sz;
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 2b73647..e8bd8d2 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -14,18 +14,18 @@
#define CONFIG_SYS_DCSRBAR 0x20000000
#define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
-#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
-#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
-#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
-#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
-#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
-#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
-#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
-#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
+#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
+#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
+#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
+#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0)
+#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
+#define CFG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000)
+#define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000)
+#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
+#define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600)
#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500)
@@ -65,7 +65,7 @@
#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
-#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000
+#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000)
@@ -165,24 +165,24 @@
unsigned long freq_qman;
};
-#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000
+#define CFG_SYS_FSL_FM1_OFFSET 0xa00000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
-#define CONFIG_SYS_FSL_FM1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
-#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000
+#define CFG_SYS_FSL_FM1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull
-#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
+#define CFG_SYS_FSL_SEC_OFFSET 0x700000ull
+#define CFG_SYS_FSL_JR0_OFFSET 0x710000ull
+#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET
#define FSL_SEC_JR1_OFFSET 0x720000ull
#define FSL_SEC_JR2_OFFSET 0x730000ull
#define FSL_SEC_JR3_OFFSET 0x740000ull
-#define CONFIG_SYS_FSL_SEC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 570397b..f1ffb23 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -9,19 +9,19 @@
#ifndef __ARCH_FSL_LSCH3_IMMAP_H_
#define __ARCH_FSL_LSCH3_IMMAP_H_
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
-#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000
-#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
-#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
+#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000)
+#define CFG_SYS_FSL_DDR3_ADDR 0x08210000
+#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000)
+#define CFG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000)
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
-#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
+#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180)
#else
-#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
+#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000)
#endif
-#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
-#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
-#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
+#define CFG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000)
+#define CFG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000)
+#define CFG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000)
#ifndef CONFIG_NXP_LSCH3_2
#define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000)
#else
@@ -29,8 +29,8 @@
#define SYS_NXP_FSPI_LUTKEY_BASE_ADDR 0x18
#define SYS_NXP_FSPI_LUT_BASE_ADDR 0x200
#endif
-#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
-#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR
+#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000)
+#define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR
#define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000)
#ifndef CONFIG_NXP_LSCH3_2
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000)
@@ -38,20 +38,20 @@
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600)
#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000
-#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000
-#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \
+#define CFG_SYS_FSL_TIMER_ADDR 0x023e0000
+#define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \
0x18A0)
-#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
-#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
+#define FSL_PMU_PCTBENR_OFFSET (CFG_SYS_FSL_PMU_ADDR + 0x8A0)
+#define FSL_LSCH3_SVR (CFG_SYS_FSL_GUTS_ADDR + 0xA4)
-#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
-#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
-#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
+#define CFG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000)
+#define CFG_SYS_FSL_WRIOP1_MDIO1 (CFG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CFG_SYS_FSL_WRIOP1_MDIO2 (CFG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CFG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
-#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
-#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
+#define CFG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL
+#define CFG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL
+#define CFG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000)
#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000)
@@ -108,16 +108,16 @@
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull
-#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET
+#define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull
+#define CFG_SYS_FSL_JR0_OFFSET 0x07010000ull
+#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET
#define FSL_SEC_JR1_OFFSET 0x07020000ull
#define FSL_SEC_JR2_OFFSET 0x07030000ull
#define FSL_SEC_JR3_OFFSET 0x07040000ull
-#define CONFIG_SYS_FSL_SEC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
#define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET)
#define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET)
#define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET)
diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h
index 3d32b7a..f569162 100644
--- a/arch/arm/include/asm/arch-imx8/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8/imx-regs.h
@@ -47,6 +47,6 @@
#define USB_BASE_ADDR 0x5b0d0000
#define USB_PHY0_BASE_ADDR 0x5b100000
-#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000)
+#define CFG_SYS_FSL_SEC_ADDR (0x31400000)
#endif /* __ASM_ARCH_IMX8_REGS_H__ */
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 29d5baa..586847f 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -87,12 +87,12 @@
#define CAAM_ARB_BASE_ADDR (0x00100000)
#define CAAM_ARB_END_ADDR (0x00107FFF)
#define CAAM_IPS_BASE_ADDR (0x30900000)
-#define CONFIG_SYS_FSL_SEC_OFFSET (0)
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET (0)
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET (0x1000)
+#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#if !defined(__ASSEMBLY__)
#include <asm/types.h>
#include <linux/bitops.h>
diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h
index 0e32828..e85918e 100644
--- a/arch/arm/include/asm/arch-ls102xa/config.h
+++ b/arch/arm/include/asm/arch-ls102xa/config.h
@@ -17,25 +17,25 @@
#define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000)
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
+#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000)
+#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000)
#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000)
-#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
-#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
-#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
+#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000)
+#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000)
+#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000)
+#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000)
#define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000)
#define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
-#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
-#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
-#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
-#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
+#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000)
+#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000)
+#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000)
+#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000)
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500)
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500)
#define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000
+#define CFG_SYS_FSL_SEC_OFFSET 0x00700000
+#define CFG_SYS_FSL_JR0_OFFSET 0x00710000
#define CONFIG_SYS_TSEC1_OFFSET 0x01d10000
#define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
index 93b0a26..fb5ded8 100644
--- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
+++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h
@@ -29,30 +29,30 @@
#define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \
SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
/* This is a bit evil since we treat rtic param as both a string & hex value */
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, 0)
+ CFG_SYS_FSL_SEC_OFFSET, 0)
struct liodn_id_table {
const char *compat;
diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 56b3a58..72944af 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -238,12 +238,12 @@
#endif
#define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET 0
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET 0x1000
+#define CFG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
#define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h
index 1e9d11b..c863cd9 100644
--- a/arch/arm/include/asm/arch-mx7/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
@@ -215,12 +215,12 @@
#define FEC_QUIRK_ENET_MAC
#define SNVS_LPGPR 0x68
-#define CONFIG_SYS_FSL_SEC_OFFSET 0
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET 0
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET 0x1000
+#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
#include <asm/mach-imx/regs-lcdif.h>
#include <asm/types.h>
diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
index ffa170f..33a699f 100644
--- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h
@@ -228,12 +228,12 @@
#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */
-#define CONFIG_SYS_FSL_SEC_OFFSET 0
-#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
- CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000
-#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
- CONFIG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_SEC_OFFSET 0
+#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
+ CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_OFFSET 0x1000
+#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \
+ CFG_SYS_FSL_JR0_OFFSET)
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32)))
#define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33)))
diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c
index 04c4b20..b65bf87 100644
--- a/arch/arm/mach-imx/cmd_dek.c
+++ b/arch/arm/mach-imx/cmd_dek.c
@@ -40,7 +40,7 @@
hab_caam_clock_enable(1);
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
+ u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
sec_init();
diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c
index ec8a875..9576b48 100644
--- a/arch/arm/mach-imx/cmd_mfgprot.c
+++ b/arch/arm/mach-imx/cmd_mfgprot.c
@@ -41,7 +41,7 @@
/* Enable HAB clock */
hab_caam_clock_enable(1);
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR +
+ u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR +
FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE)
diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c
index 304a030..88f6fe0 100644
--- a/arch/arm/mach-imx/mx7/clock.c
+++ b/arch/arm/mach-imx/mx7/clock.c
@@ -30,9 +30,9 @@
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c
index 6191153..37d8565 100644
--- a/arch/arm/mach-imx/mx7ulp/clock.c
+++ b/arch/arm/mach-imx/mx7ulp/clock.c
@@ -18,9 +18,9 @@
int get_clocks(void)
{
#ifdef CONFIG_FSL_ESDHC_IMX
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
#endif
#endif
diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c
index b729187..0e81cc8 100644
--- a/arch/arm/mach-imx/speed.c
+++ b/arch/arm/mach-imx/speed.c
@@ -21,21 +21,21 @@
{
#ifdef CONFIG_FSL_ESDHC_IMX
#ifdef CONFIG_FSL_USDHC
-#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
#endif
#else
-#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
+#if CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
-#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
+#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
#else
gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index ff73596..ed89011 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -84,7 +84,7 @@
static void check_erratum_a4580(uint32_t svr)
{
const serdes_corenet_t __iomem *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
unsigned int lane;
for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 432d4b1..49a1aac 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -98,7 +98,7 @@
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
if (SVR_SOC_VER(svr) == SVR_T4080) {
ccsr_rcpm_t *rcpm =
- (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ (void __iomem *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
FSL_CORENET_DEVDISR2_DTSEC1_9);
@@ -540,16 +540,16 @@
for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) {
switch (i) {
case 0:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR_ADDR;
break;
-#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
+#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR2_ADDR;
break;
#endif
-#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
+#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
- ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
+ ddr[i] = (void *)CFG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 9fb7802..47bea51 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -160,7 +160,7 @@
{
int i;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) {
@@ -217,7 +217,7 @@
char cpc_subarg[16];
bool have_hwconfig = false;
int cpc_args = 0;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
/* Extract hwconfig from environment */
ret = env_get_f("hwconfig", buffer, sizeof(buffer));
@@ -271,7 +271,7 @@
static void invalidate_cpc(void)
{
int i;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
/* skip CPC when it used as all SRAM */
@@ -300,7 +300,7 @@
static void corenet_tb_init(void)
{
volatile ccsr_rcpm_t *rcpm =
- (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
volatile ccsr_pic_t *pic =
(void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
u32 whoami = in_be32(&pic->whoami);
@@ -476,7 +476,7 @@
do {
int j, cluster_valid = 0;
- l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
+ l2cache = (void __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
cluster = in_be32(&gur->tp_cluster[i].lower);
@@ -518,7 +518,7 @@
#ifdef CONFIG_L2_CACHE
ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR;
#elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
- struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2;
+ struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2;
#endif
puts ("L2: ");
@@ -664,7 +664,7 @@
const char *spin;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571
- ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
#endif
#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \
defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011)
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 811e6d6..1161938 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -164,7 +164,7 @@
static inline void ft_fixup_l3cache(void *blob, int off)
{
u32 line_size, num_ways, size, num_sets;
- cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR;
+ cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR;
u32 cfg0 = in_be32(&cpc->cpccfg0);
size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC;
@@ -299,7 +299,7 @@
u32 l2cfg0 = mfspr(SPRN_L2CFG0);
#else
struct ccsr_cluster_l2 *l2cache =
- (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2);
+ (struct ccsr_cluster_l2 __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2);
u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
#endif
u32 size, line_size, num_ways, num_sets;
@@ -466,11 +466,11 @@
get_sys_info(&sysinfo);
#ifdef CONFIG_SYS_DPAA_FMAN
- ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET,
+ ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET,
sysinfo.freq_fman[0]);
#if (CONFIG_SYS_NUM_FMAN == 2)
- ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET,
+ ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET,
sysinfo.freq_fman[1]);
#endif
#endif
@@ -611,7 +611,7 @@
else {
ccsr_sec_t __iomem *sec;
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 1a30395..3a6ce32 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -21,10 +21,10 @@
#ifdef CONFIG_SYS_FSL_SRDS_2
static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT];
#endif
@@ -104,13 +104,13 @@
ret |= serdes2_prtcl_map[device];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
if (!serdes3_prtcl_map[NONE])
fsl_serdes_init();
ret |= serdes3_prtcl_map[device];
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
if (!serdes4_prtcl_map[NONE])
fsl_serdes_init();
@@ -139,13 +139,13 @@
cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
break;
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
case FSL_SRDS_3:
cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL;
cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT;
break;
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
case FSL_SRDS_4:
cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL;
cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT;
@@ -351,28 +351,28 @@
#ifdef CONFIG_SYS_FSL_SRDS_1
serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL,
FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT,
serdes1_prtcl_map);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL,
FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT,
serdes2_prtcl_map);
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_3
+#ifdef CFG_SYS_FSL_SRDS_3
serdes_init(FSL_SRDS_3,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL,
FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT,
serdes3_prtcl_map);
#endif
-#ifdef CONFIG_SYS_FSL_SRDS_4
+#ifdef CFG_SYS_FSL_SRDS_4
serdes_init(FSL_SRDS_4,
- CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
+ CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL,
FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT,
serdes4_prtcl_map);
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
index 1d35733..437ecde 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c
@@ -109,7 +109,7 @@
int serdes_lane_enabled(int lane)
{
ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
int bank = lanes[lane].bank;
int word = lanes[lane].lpd / 32;
@@ -257,7 +257,7 @@
if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0))
return;
- regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ regs = (typeof(regs))CFG_SYS_FSL_CORENET_SERDES_ADDR;
prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
__serdes_reset_rx(regs, prtcl, device);
@@ -466,7 +466,7 @@
static void wait_for_rstdone(unsigned int bank)
{
serdes_corenet_t *srds_regs =
- (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
unsigned long long end_tick;
u32 rstctl;
@@ -527,7 +527,7 @@
if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN))
return;
- srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
@@ -601,7 +601,7 @@
serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2;
break;
default:
- srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+ srds2_regs = (void *)CFG_SYS_FSL_CORENET_SERDES2_ADDR;
/* We don't need bank 4, so power it down */
setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD);
diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c
index 34974c9..9ad48d4 100644
--- a/arch/powerpc/cpu/mpc85xx/liodn.c
+++ b/arch/powerpc/cpu/mpc85xx/liodn.c
@@ -76,7 +76,7 @@
static void setup_sec_liodn_base(void)
{
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR;
+ ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR;
u32 base;
if (!IS_E_PROCESSOR(get_svr()))
@@ -101,12 +101,12 @@
switch(dev) {
case FSL_HW_PORTAL_FMAN1:
- fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+ fm = (void *)CFG_SYS_FSL_FM1_ADDR;
break;
#if (CONFIG_SYS_NUM_FMAN == 2)
case FSL_HW_PORTAL_FMAN2:
- fm = (void *)CONFIG_SYS_FSL_FM2_ADDR;
+ fm = (void *)CFG_SYS_FSL_FM2_ADDR;
break;
#endif
default:
@@ -130,7 +130,7 @@
static void setup_pme_liodn_base(void)
{
#ifdef CONFIG_SYS_DPAA_PME
- ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR;
+ ccsr_pme_t *pme = (void *)CFG_SYS_FSL_CORENET_PME_ADDR;
u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) |
liodn_bases[FSL_HW_PORTAL_PME].id[1];
@@ -141,7 +141,7 @@
#ifdef CONFIG_SYS_FSL_RAID_ENGINE
static void setup_raide_liodn_base(void)
{
- struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR;
+ struct ccsr_raide *raide = (void *)CFG_SYS_FSL_RAID_ENGINE_ADDR;
/* setup raid engine liodn base for data/desc ; both set to 47 */
u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) |
@@ -155,7 +155,7 @@
static void set_rman_liodn(struct liodn_id_table *tbl, int size)
{
int i;
- struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
+ struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
for (i = 0; i < size; i++) {
/* write the RMan block number */
@@ -168,7 +168,7 @@
static void setup_rman_liodn_base(struct liodn_id_table *tbl, int size)
{
int i;
- struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR;
+ struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
u32 base = liodn_bases[FSL_HW_PORTAL_RMAN].id[0];
out_be32(&rman->mmliodnbr, base);
diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c
index e1469eb..f109ecb 100644
--- a/arch/powerpc/cpu/mpc85xx/mp.c
+++ b/arch/powerpc/cpu/mpc85xx/mp.c
@@ -265,8 +265,8 @@
struct law_entry e;
gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
- ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR);
- rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+ ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR);
+ rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
whoami = in_be32(&pic->whoami);
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index a7004a6..31d0481 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -26,14 +26,14 @@
{
volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_FSL_CORENET
- volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
+ volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
#ifdef CONFIG_HETROGENOUS_CLUSTERS
unsigned int dsp_cpu;
uint rcw_tmp1, rcw_tmp2;
#endif
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
- int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
+ int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS;
#endif
__maybe_unused u32 svr;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 024414e..5341756 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -966,7 +966,7 @@
erratum_set_dcsr 0xb0e38 0xe0400000
erratum_set_dcsr 0xb0008 0x00900000
erratum_set_dcsr 0xb0e40 0xe00a0000
- erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
+ erratum_set_ccsr 0x18600 CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
#ifdef CONFIG_RAMBOOT_PBL
erratum_set_ccsr 0x10f00 0x495e5000
#else
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index 4e3f900..dd27416 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -20,7 +20,7 @@
#define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
#ifdef CONFIG_FSL_CORENET
-#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
+#define LAW_BASE (CFG_SYS_FSL_CORENET_CCM_ADDR)
#define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
#define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
#define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index 62524a2..c815d19 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -79,9 +79,9 @@
int idx, first, last;
u32 i;
unsigned long long end_tick;
- struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio_regs = (void *)CFG_SYS_FSL_SRIO_ADDR;
- srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR);
+ srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR);
conf_lane = (in_be32((void *)&srds_regs->srdspccr0)
>> (12 - port * 4)) & 0x3;
init_lane = (in_be32((void *)&srio_regs->lp_serial
@@ -291,7 +291,7 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
void srio_boot_master(int port)
{
- struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */
out_be32((void *)&srio->impl.port[port - 1].ptaacr,
@@ -343,7 +343,7 @@
void srio_boot_master_release_slave(int port)
{
- struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR;
+ struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
u32 escsr;
debug("SRIOBOOT - MASTER: "
"Check the port status and release slave core ...\n");
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index d3d4e9c..25d1b48 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -17,10 +17,10 @@
#include <fsl_ddrc_version.h>
#if defined(CONFIG_ARCH_MPC8548)
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 1
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P1010)
#define CONFIG_FSL_SDHC_V2_3
@@ -59,30 +59,30 @@
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_P2020)
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041)
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */
#define CONFIG_SYS_NUM_FMAN 2
@@ -91,11 +91,11 @@
#define CONFIG_SYS_NUM_FM1_10GEC 1
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
-#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5040)
#define CONFIG_SYS_NUM_FMAN 2
@@ -104,7 +104,7 @@
#define CONFIG_SYS_NUM_FM2_DTSEC 5
#define CONFIG_SYS_NUM_FM2_10GEC 1
#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
-#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
+#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131)
#define CONFIG_FSL_SDHC_V2_3
@@ -118,7 +118,7 @@
#elif defined(CONFIG_ARCH_T4240)
#ifdef CONFIG_ARCH_T4240
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 2
#define CONFIG_SYS_NUM_FM2_DTSEC 8
@@ -131,17 +131,17 @@
#endif
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_FSL_SRDS_3
-#define CONFIG_SYS_FSL_SRDS_4
+#define CFG_SYS_FSL_SRDS_3
+#define CFG_SYS_FSL_SRDS_4
#define CONFIG_SYS_NUM_FMAN 2
#define CONFIG_SYS_PME_CLK 0
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
#define CONFIG_SYS_FM1_CLK 3
#define CONFIG_SYS_FM2_CLK 3
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
#define CONFIG_SYS_FSL_SRDS_1
@@ -154,21 +154,21 @@
#ifdef CONFIG_ARCH_B4860
#define CONFIG_MAX_DSP_CPUS 12
#define CONFIG_NUM_DSP_CPUS 6
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
#define CONFIG_SYS_NUM_FM1_10GEC 2
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#else
#define CONFIG_MAX_DSP_CPUS 2
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 4
#define CONFIG_SYS_NUM_FM1_10GEC 0
#endif
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042)
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 5
@@ -184,8 +184,7 @@
#define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T1024)
-#define CONFIG_SYS_FSL_NUM_CC_PLL 2
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 }
#define CONFIG_SYS_FSL_SRDS_1
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 4
@@ -202,15 +201,15 @@
#elif defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FMAN 1
-#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
+#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_FSL_SRDS_1
#if defined(CONFIG_ARCH_T2080)
#define CONFIG_SYS_NUM_FM1_DTSEC 8
#define CONFIG_SYS_NUM_FM1_10GEC 4
#define CONFIG_SYS_FSL_SRDS_2
-#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
-#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
-#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
+#define CFG_SYS_FSL_SRIO_MAX_PORTS 2
+#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9
+#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#endif
#define CONFIG_PME_PLAT_CLK_DIV 1
#define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV
@@ -224,7 +223,7 @@
#define CONFIG_FSL_SDHC_V2_3
#define CONFIG_TSECV2_1
#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8
-#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000
+#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#endif
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h
index be55f99..de85bcf 100644
--- a/arch/powerpc/include/asm/fsl_liodn.h
+++ b/arch/powerpc/include/asm/fsl_liodn.h
@@ -33,7 +33,7 @@
{ .id = { id_a }, .num_ids = 1, .portid = port, \
.reg_offset[0] = offsetof(struct ccsr_rio, liodn) \
+ (port - 1) * 0x200 \
- + CONFIG_SYS_FSL_SRIO_ADDR, \
+ + CFG_SYS_FSL_SRIO_ADDR, \
}
struct liodn_id_table {
@@ -130,29 +130,29 @@
#define SET_QMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,qman", liodn, \
offsetof(struct ccsr_qman, liodnr) + \
- CONFIG_SYS_FSL_QMAN_OFFSET, \
- CONFIG_SYS_FSL_QMAN_OFFSET)
+ CFG_SYS_FSL_QMAN_OFFSET, \
+ CFG_SYS_FSL_QMAN_OFFSET)
#define SET_BMAN_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,bman", liodn, \
offsetof(struct ccsr_bman, liodnr) + \
- CONFIG_SYS_FSL_BMAN_OFFSET, \
- CONFIG_SYS_FSL_BMAN_OFFSET)
+ CFG_SYS_FSL_BMAN_OFFSET, \
+ CFG_SYS_FSL_BMAN_OFFSET)
#define SET_PME_LIODN(liodn) \
SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \
- CONFIG_SYS_FSL_CORENET_PME_OFFSET, \
- CONFIG_SYS_FSL_CORENET_PME_OFFSET)
+ CFG_SYS_FSL_CORENET_PME_OFFSET, \
+ CFG_SYS_FSL_CORENET_PME_OFFSET)
#define SET_PMAN_LIODN(num, liodn) \
SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \
offsetof(struct ccsr_pman, ppa1) + \
- CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
- CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
+ CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \
+ CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
/* -1 from portID due to how immap has the registers */
#define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \
- CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \
+ CFG_SYS_FSL_FM##fmNum##_OFFSET + \
offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
#ifdef CONFIG_SYS_FMAN_V3
@@ -160,31 +160,31 @@
#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
#else
/* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */
#define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */
#define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \
SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \
liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \
- CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
+ CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
#endif
/*
* handle both old and new versioned SEC properties:
@@ -193,44 +193,44 @@
#define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \
SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \
SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\
offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
/* This is a bit evil since we treat rtic param as both a string & hex value */
#define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \
SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \
SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \
liodnA, \
offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, \
- CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
+ CFG_SYS_FSL_SEC_OFFSET, \
+ CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \
SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \
offsetof(ccsr_sec_t, decoliodnr[num].ls) + \
- CONFIG_SYS_FSL_SEC_OFFSET, 0)
+ CFG_SYS_FSL_SEC_OFFSET, 0)
#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \
SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \
liodnA, \
offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \
- CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \
+ CFG_SYS_FSL_RAID_ENGINE_OFFSET, \
offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \
- CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
+ CFG_SYS_FSL_RAID_ENGINE_OFFSET)
#define SET_RMAN_LIODN(ibNum, liodn) \
SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \
offsetof(struct ccsr_rman, mmitdr) + \
- CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \
- CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
+ CFG_SYS_FSL_CORENET_RMAN_OFFSET, \
+ CFG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[];
extern struct liodn_id_table raide_liodn_tbl[];
diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 0bf5b9c..8e18202 100644
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -862,7 +862,7 @@
};
#define CFG_SYS_MPC8xxx_DDR_OFFSET (0x2000)
-#define CONFIG_SYS_FSL_DDR_ADDR \
+#define CFG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
#define CFG_SYS_MPC83xx_DMA_OFFSET (0x8000)
#define CFG_SYS_MPC83xx_DMA_ADDR \
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7a7a7f2..c9ced54 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -963,7 +963,7 @@
u32 prtoccsr; /* Port Response Time-out CCSR */
u8 res1[20];
u32 pgccsr; /* Port General CSR */
- struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_lp_serial_port port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Logical error reporting registers */
@@ -993,7 +993,7 @@
/* Physical error reporting registers */
struct rio_phys_err {
- struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_phys_err_port port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Implementation Space: General Port-Common */
@@ -1033,7 +1033,7 @@
/* Implementation Space: register */
struct rio_implement {
struct rio_impl_common com;
- struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_impl_port_spec port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
/* Revision Control Register */
@@ -1061,13 +1061,13 @@
/* ATMU window registers */
struct rio_atmu_win {
- struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM];
+ struct rio_atmu_row outbw[CFG_SYS_FSL_SRIO_OB_WIN_NUM];
u8 res0[64];
- struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM];
+ struct rio_atmu_riw inbw[CFG_SYS_FSL_SRIO_IB_WIN_NUM];
};
struct rio_atmu {
- struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_atmu_win port[CFG_SYS_FSL_SRIO_MAX_PORTS];
};
#ifdef CONFIG_SYS_FSL_RMU
@@ -1154,7 +1154,7 @@
struct rio_atmu atmu;
#ifdef CONFIG_SYS_FSL_RMU
u8 res5[8192];
- struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM];
+ struct rio_msg msg[CFG_SYS_FSL_SRIO_MSG_UNIT_NUM];
u8 res6[512];
struct rio_dbell dbell;
u8 res7[100];
@@ -1162,7 +1162,7 @@
#endif
#ifdef CONFIG_SYS_FSL_SRIO_LIODN
u8 res5[8192];
- struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS];
+ struct rio_liodn liodn[CFG_SYS_FSL_SRIO_MAX_PORTS];
#endif
};
#endif
@@ -2431,17 +2431,17 @@
#endif
#ifdef CONFIG_FSL_CORENET
-#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
+#define CFG_SYS_FSL_CORENET_CCM_OFFSET 0x0000
#ifdef CONFIG_SYS_PMAN
-#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
-#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
-#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
+#define CFG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000
+#define CFG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000
+#define CFG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000
#endif
#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x8000
#define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x9000
#define CFG_SYS_MPC8xxx_DDR3_OFFSET 0xA000
-#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
-#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
+#define CFG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000
+#define CFG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000
#ifdef CONFIG_SYS_FSL_SFP_VER_3_0
/* In SFPv3, OSPR register is now at offset 0x200.
* * So directly mapping sfp register map to this address */
@@ -2450,13 +2450,13 @@
#else
#define CONFIG_SYS_SFP_OFFSET 0xE8000
#endif
-#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
-#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
-#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
-#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
-#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000
-#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000
-#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000
+#define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000
+#define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000
+#define CFG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000
+#define CFG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000
+#define CFG_SYS_FSL_CPC_OFFSET 0x10000
+#define CFG_SYS_FSL_SCFG_OFFSET 0xFC000
+#define CFG_SYS_FSL_PAMU_OFFSET 0x20000
#define CFG_SYS_MPC85xx_DMA1_OFFSET 0x100000
#define CFG_SYS_MPC85xx_DMA2_OFFSET 0x101000
#define CFG_SYS_MPC85xx_DMA3_OFFSET 0x102000
@@ -2468,7 +2468,7 @@
#define CFG_SYS_MPC85xx_GPIO_OFFSET 0x130000
#define CFG_SYS_MPC85xx_TDM_OFFSET 0x185000
#define CFG_SYS_MPC85xx_QE_OFFSET 0x140000
-#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
+#define CFG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000
#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
!defined(CONFIG_ARCH_B4420)
#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x240000
@@ -2487,33 +2487,33 @@
#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100
#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x220000
#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000
+#define CFG_SYS_FSL_SEC_OFFSET 0x300000
+#define CFG_SYS_FSL_JR0_OFFSET 0x301000
#define CONFIG_SYS_SEC_MON_OFFSET 0x314000
-#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
-#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
-#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
-#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
-#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
-#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
-#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
-#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
-#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
-#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
-#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
-#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
-#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
-#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000
-#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
-#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
-#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
-#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
-#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
-#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
-#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
-#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
-#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
+#define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000
+#define CFG_SYS_FSL_QMAN_OFFSET 0x318000
+#define CFG_SYS_FSL_BMAN_OFFSET 0x31a000
+#define CFG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000
+#define CFG_SYS_FSL_FM1_OFFSET 0x400000
+#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
+#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
+#define CFG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000
+#define CFG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000
+#define CFG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000
+#define CFG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000
+#define CFG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000
+#define CFG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000
+#define CFG_SYS_FSL_FM2_OFFSET 0x500000
+#define CFG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000
+#define CFG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000
+#define CFG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000
+#define CFG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000
+#define CFG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000
+#define CFG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000
+#define CFG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000
+#define CFG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000
+#define CFG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000
#else
#define CFG_SYS_MPC85xx_ECM_OFFSET 0x0000
#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x2000
@@ -2551,57 +2551,57 @@
#define CONFIG_SYS_MDIO1_OFFSET 0x24000
#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000
#if defined(CONFIG_ARCH_C29X)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000
+#define CFG_SYS_FSL_SEC_OFFSET 0x80000
+#define CFG_SYS_FSL_JR0_OFFSET 0x81000
#else
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000
-#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000
+#define CFG_SYS_FSL_SEC_OFFSET 0x30000
+#define CFG_SYS_FSL_JR0_OFFSET 0x31000
#endif
#define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CONFIG_SYS_SEC_MON_OFFSET 0xE6000
#define CONFIG_SYS_SFP_OFFSET 0xE7000
-#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
-#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
-#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
-#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
-#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
+#define CFG_SYS_FSL_QMAN_OFFSET 0x88000
+#define CFG_SYS_FSL_BMAN_OFFSET 0x8a000
+#define CFG_SYS_FSL_FM1_OFFSET 0x100000
+#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
+#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
+#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
#endif
#define CFG_SYS_MPC85xx_PIC_OFFSET 0x40000
#define CFG_SYS_MPC85xx_GUTS_OFFSET 0xE0000
-#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
+#define CFG_SYS_FSL_SRIO_OFFSET 0xC0000
-#define CONFIG_SYS_FSL_CPC_ADDR \
- (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
-#define CONFIG_SYS_FSL_SCFG_ADDR \
- (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET)
-#define CONFIG_SYS_FSL_QMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
-#define CONFIG_SYS_FSL_BMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
-#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET)
+#define CFG_SYS_FSL_CPC_ADDR \
+ (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET)
+#define CFG_SYS_FSL_SCFG_ADDR \
+ (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET)
+#define CFG_SYS_FSL_QMAN_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET)
+#define CFG_SYS_FSL_BMAN_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_BMAN_OFFSET)
+#define CFG_SYS_FSL_CORENET_PME_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_PME_OFFSET)
+#define CFG_SYS_FSL_RAID_ENGINE_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_RAID_ENGINE_OFFSET)
+#define CFG_SYS_FSL_CORENET_RMAN_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RMAN_OFFSET)
#define CFG_SYS_MPC85xx_GUTS_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
+#define CFG_SYS_FSL_CORENET_CCM_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CCM_OFFSET)
+#define CFG_SYS_FSL_CORENET_CLK_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CLK_OFFSET)
+#define CFG_SYS_FSL_CORENET_RCPM_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RCPM_OFFSET)
#define CFG_SYS_MPC85xx_ECM_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET)
-#define CONFIG_SYS_FSL_DDR_ADDR \
+#define CFG_SYS_FSL_DDR_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET)
-#define CONFIG_SYS_FSL_DDR2_ADDR \
+#define CFG_SYS_FSL_DDR2_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET)
-#define CONFIG_SYS_FSL_DDR3_ADDR \
+#define CFG_SYS_FSL_DDR3_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET)
@@ -2631,14 +2631,14 @@
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET)
#define CFG_SYS_MPC85xx_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES2_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES3_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES3_OFFSET)
+#define CFG_SYS_FSL_CORENET_SERDES4_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES4_OFFSET)
#define CFG_SYS_MPC85xx_USB1_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET)
#define CFG_SYS_MPC85xx_USB2_ADDR \
@@ -2647,20 +2647,20 @@
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET)
#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET)
-#define CONFIG_SYS_FSL_SEC_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
-#define CONFIG_SYS_FSL_JR0_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
-#define CONFIG_SYS_FSL_FM1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET)
-#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
-#define CONFIG_SYS_FSL_FM2_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET)
-#define CONFIG_SYS_FSL_SRIO_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET)
+#define CFG_SYS_FSL_SEC_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET)
+#define CFG_SYS_FSL_JR0_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET)
+#define CFG_SYS_FSL_FM1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET)
+#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
+#define CFG_SYS_FSL_FM2_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET)
+#define CFG_SYS_FSL_SRIO_ADDR \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET)
#define CONFIG_SYS_PAMU_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \
(CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET)
@@ -2739,8 +2739,8 @@
u32 l2erraddr; /* 0xe54 L2 cache error address */
u32 l2errctl; /* 0xe58 L2 cache error control */
};
-#define CONFIG_SYS_FSL_CLUSTER_1_L2 \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET)
+#define CFG_SYS_FSL_CLUSTER_1_L2 \
+ (CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET)
#endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000