global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c
index 86b5b21..4e1fe28 100644
--- a/arch/arm/cpu/armv7/ls102xa/clock.c
+++ b/arch/arm/cpu/armv7/ls102xa/clock.c
@@ -15,8 +15,8 @@
void get_sys_info(struct sys_info *sys_info)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
- struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR);
unsigned int cpu;
const u8 core_cplx_pll[6] = {
[0] = 0, /* CC1 PPL / 1 */
diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c
index 0b3e3b2..d530e06 100644
--- a/arch/arm/cpu/armv7/ls102xa/cpu.c
+++ b/arch/arm/cpu/armv7/ls102xa/cpu.c
@@ -228,7 +228,7 @@
uint get_svr(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return in_be32(&gur->svr);
}
@@ -237,7 +237,7 @@
int print_cpuinfo(void)
{
char buf1[32], buf2[32];
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major, minor, ver, i;
svr = in_be32(&gur->svr);
@@ -316,7 +316,7 @@
void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *rcpm2_base =
(void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
- struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
u32 state;
icache_enable();
@@ -355,7 +355,7 @@
/* Set the address at which the secondary core starts from.*/
void smp_set_core_boot_addr(unsigned long addr, int corenr)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->scratchrw[0], addr);
}
@@ -363,7 +363,7 @@
/* Release the secondary core from holdoff state and kick it */
void smp_kick_all_cpus(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->brrl, 0x2);
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c
index 83f9882..c01cebb 100644
--- a/arch/arm/cpu/armv7/ls102xa/fdt.c
+++ b/arch/arm/cpu/armv7/ls102xa/fdt.c
@@ -92,7 +92,7 @@
int off;
int val;
const char *sysclk_path;
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr;
svr = in_be32(&gur->svr);
@@ -105,7 +105,7 @@
else {
ccsr_sec_t __iomem *sec;
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
+ sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR;
fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
}
#endif
diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
index caf51e1..f74d819 100644
--- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
+++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c
@@ -39,7 +39,7 @@
int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u32 cfg = in_be32(&gur->rcwsr[4]);
int i;
@@ -74,7 +74,7 @@
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
@@ -103,14 +103,14 @@
#ifdef CONFIG_SYS_FSL_SRDS_1
if (!(serdes1_prtcl_map & (1ULL << NONE)))
serdes1_prtcl_map = serdes_init(FSL_SRDS_1,
- CONFIG_SYS_FSL_SERDES_ADDR,
+ CFG_SYS_FSL_SERDES_ADDR,
RCWSR4_SRDS1_PRTCL_MASK,
RCWSR4_SRDS1_PRTCL_SHIFT);
#endif
#ifdef CONFIG_SYS_FSL_SRDS_2
if (!(serdes2_prtcl_map & (1ULL << NONE)))
serdes2_prtcl_map = serdes_init(FSL_SRDS_2,
- CONFIG_SYS_FSL_SERDES_ADDR +
+ CFG_SYS_FSL_SERDES_ADDR +
FSL_SRDS_2 * 0x1000,
RCWSR4_SRDS2_PRTCL_MASK,
RCWSR4_SRDS2_PRTCL_SHIFT);
diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
index 28a7945..b4d113d 100644
--- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
+++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c
@@ -31,7 +31,7 @@
{
const char *src = (const char *)CONFIG_SYS_SDRAM_BASE;
char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN);
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
int i;
out_le32(&scfg->sparecr[2], dest);
@@ -57,8 +57,8 @@
static void __secure ls1_deepsleep_irq_cfg(void)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
/* Mask interrupts from GIC */
@@ -120,8 +120,8 @@
{
void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR;
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Set HRSTCR */
setbits_be32(&scfg->hrstcr, 0x80000000);
@@ -155,9 +155,9 @@
static void __secure ls1_deep_sleep(u32 entry_point)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;
void *qixis_base = (void *)QIXIS_BASE;
@@ -213,8 +213,8 @@
#else
static void __secure ls1_sleep(void)
{
- struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
- struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR;
+ struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE
u32 tmp;
diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S
index 3956178..e7c4fbf 100644
--- a/arch/arm/cpu/armv7/ls102xa/psci.S
+++ b/arch/arm/cpu/armv7/ls102xa/psci.S
@@ -129,8 +129,8 @@
mov r1, r4
@ Get DCFG base address
- movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+ movw r4, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+ movt r4, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
@ Detect target CPU state
ldr r2, [r4, #DCFG_CCSR_BRR]
@@ -141,8 +141,8 @@
@ Reset target CPU
@ Get SCFG base address
- movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
- movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
+ movw r0, #(CFG_SYS_FSL_SCFG_ADDR & 0xffff)
+ movt r0, #(CFG_SYS_FSL_SCFG_ADDR >> 16)
@ Enable CORE Soft Reset
movw r5, #0
@@ -216,8 +216,8 @@
mov r1, r4
@ Get RCPM base address
- movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16)
+ movw r4, #(CFG_SYS_FSL_RCPM_ADDR & 0xffff)
+ movt r4, #(CFG_SYS_FSL_RCPM_ADDR >> 16)
mov r0, #PSCI_AFFINITY_LEVEL_ON
@@ -236,8 +236,8 @@
.globl psci_system_reset
psci_system_reset:
@ Get DCFG base address
- movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
+ movw r1, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff)
+ movt r1, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
mov r2, #DCFG_CCSR_RSTCR_RESET_REQ
rev r2, r2
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 728efc4..1dafa3c 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -54,7 +54,7 @@
unsigned int get_soc_major_rev(void)
{
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
+ struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
unsigned int svr, major;
svr = in_be32(&gur->svr);
@@ -113,7 +113,7 @@
/* part 1 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* disables propagation of barrier transactions to DDRC from CCI400 */
out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER);
@@ -129,7 +129,7 @@
/* part 2 of 2 */
struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
- struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
+ struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
u32 tmp;
/* enable propagation of barrier transactions to DDRC from CCI400 */
@@ -161,7 +161,7 @@
int arch_soc_init(void)
{
- struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
+ struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
CONFIG_SYS_CCI400_OFFSET);
unsigned int major;