| // SPDX-License-Identifier: GPL-2.0 |
| * dts file for Xilinx ZynqMP R5 |
| * (C) Copyright 2018, Xilinx, Inc. |
| * Michal Simek <michal.simek@amd.com> |
| compatible = "xlnx,zynqmp-r5"; |
| model = "Xilinx ZynqMP R5"; |
| compatible = "arm,cortex-r5"; |
| reg = <0x00000000 0x20000000>; |
| stdout-path = "serial0:115200n8"; |
| compatible = "fixed-clock"; |
| clock-frequency = <100000000>; |
| compatible = "simple-bus"; |
| reg = <0xff110000 0x1000>; |
| compatible = "cdns,uart-r1p12", "xlnx,xuartps"; |
| reg = <0xff010000 0x1000>; |
| clock-names = "uart_clk", "pclk"; |
| clocks = <&clk100 &clk100>; |