// SPDX-License-Identifier: GPL-2.0+ | |
/* | |
* Copyright 2018 NXP | |
*/ | |
#include <dt-bindings/clock/imx8qxp-clock.h> | |
#include <dt-bindings/interrupt-controller/arm-gic.h> | |
/{ | |
cpus { | |
#address-cells = <2>; | |
#size-cells = <0>; | |
/* We have 1 clusters having 4 Cortex-A35 cores */ | |
A35_0: cpu@0 { | |
device_type = "cpu"; | |
compatible = "arm,cortex-a35"; | |
reg = <0x0 0x0>; | |
enable-method = "psci"; | |
next-level-cache = <&A35_L2>; | |
#cooling-cells = <2>; | |
}; | |
A35_1: cpu@1 { | |
device_type = "cpu"; | |
compatible = "arm,cortex-a35"; | |
reg = <0x0 0x1>; | |
enable-method = "psci"; | |
next-level-cache = <&A35_L2>; | |
#cooling-cells = <2>; | |
}; | |
A35_2: cpu@2 { | |
device_type = "cpu"; | |
compatible = "arm,cortex-a35"; | |
reg = <0x0 0x2>; | |
enable-method = "psci"; | |
next-level-cache = <&A35_L2>; | |
#cooling-cells = <2>; | |
}; | |
A35_3: cpu@3 { | |
device_type = "cpu"; | |
compatible = "arm,cortex-a35"; | |
reg = <0x0 0x3>; | |
enable-method = "psci"; | |
next-level-cache = <&A35_L2>; | |
#cooling-cells = <2>; | |
}; | |
A35_L2: l2-cache0 { | |
compatible = "cache"; | |
}; | |
}; | |
pmu { | |
compatible = "arm,armv8-pmuv3"; | |
interrupts = <GIC_PPI 7 | |
(GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; | |
interrupt-affinity = <&A35_0>, <&A35_1>, <&A35_2>, <&A35_3>; | |
}; | |
psci { | |
compatible = "arm,psci-1.0"; | |
method = "smc"; | |
cpu_suspend = <0xc4000001>; | |
cpu_off = <0xc4000002>; | |
cpu_on = <0xc4000003>; | |
}; | |
}; |