| /* SPDX-License-Identifier: GPL-2.0+ */ |
| * Copyright 2016 Freescale Semiconductor, Inc. |
| #if defined(CONFIG_ARCH_MX7ULP) || defined(CONFIG_ARCH_IMX8) || \ |
| defined(CONFIG_ARCH_IMXRT) || defined(CONFIG_ARCH_IMX8ULP) || defined(CONFIG_ARCH_IMX9) |
| struct lpuart_fsl_reg32 { |
| struct lpuart_fsl_reg32 { |
| #define LPUART_BAUD_BOTHEDGE_MASK (0x20000) |
| #define LPUART_BAUD_OSR_MASK (0x1F000000) |
| #define LPUART_BAUD_OSR_SHIFT (24) |
| #define LPUART_BAUD_OSR(x) ((((uint32_t)(x)) << 24) & 0x1F000000) |
| #define LPUART_BAUD_SBR_MASK (0x1FFF) |
| #define LPUART_BAUD_SBR_SHIFT (0U) |
| #define LPUART_BAUD_SBR(x) (((uint32_t)(x)) & 0x1FFF) |
| #define LPUART_BAUD_M10_MASK (0x20000000U) |
| #define LPUART_BAUD_SBNS_MASK (0x2000U) |