clk: rockchip: rk3308: Support reading UART rate and clock registers
Add support to read RK3308 registers used to configure UART clocks, and
thus to get UART rate and baudrate. This fixes clock_get_rate returning
error on serial device probing. Moreover, there is no need anymore to
use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files
for all cases where UART is not inited by U-Boot proper or by SPL o by
TPL code but by a preliminary external boot phase (for Rock PI S, UART
is inited by external TPL).
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
diff --git a/drivers/clk/rockchip/clk_rk3308.c b/drivers/clk/rockchip/clk_rk3308.c
index d27673c..d0a3f65 100644
--- a/drivers/clk/rockchip/clk_rk3308.c
+++ b/drivers/clk/rockchip/clk_rk3308.c
@@ -451,6 +451,58 @@
return rk3308_pwm_get_clk(clk);
}
+static ulong rk3308_uart_get_clk(struct clk *clk)
+{
+ struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
+ struct rk3308_cru *cru = priv->cru;
+ u32 div, pll_sel, con, con_id, parent;
+
+ switch (clk->id) {
+ case SCLK_UART0:
+ con_id = 10;
+ break;
+ case SCLK_UART1:
+ con_id = 13;
+ break;
+ case SCLK_UART2:
+ con_id = 16;
+ break;
+ case SCLK_UART3:
+ con_id = 19;
+ break;
+ case SCLK_UART4:
+ con_id = 22;
+ break;
+ default:
+ printf("do not support this uart interface\n");
+ return -EINVAL;
+ }
+
+ con = readl(&cru->clksel_con[con_id]);
+ pll_sel = (con & CLK_UART_PLL_SEL_MASK) >> CLK_UART_PLL_SEL_SHIFT;
+ div = (con & CLK_UART_DIV_CON_MASK) >> CLK_UART_DIV_CON_SHIFT;
+
+ switch (pll_sel) {
+ case CLK_UART_PLL_SEL_DPLL:
+ parent = priv->dpll_hz;
+ break;
+ case CLK_UART_PLL_SEL_VPLL0:
+ parent = priv->vpll0_hz;
+ break;
+ case CLK_UART_PLL_SEL_VPLL1:
+ parent = priv->vpll0_hz;
+ break;
+ case CLK_UART_PLL_SEL_24M:
+ parent = OSC_HZ;
+ break;
+ default:
+ printf("do not support this uart pll sel\n");
+ return -EINVAL;
+ }
+
+ return DIV_TO_RATE(parent, div);
+}
+
static ulong rk3308_vop_get_clk(struct clk *clk)
{
struct rk3308_clk_priv *priv = dev_get_priv(clk->dev);
@@ -813,6 +865,13 @@
case SCLK_EMMC_SAMPLE:
rate = rk3308_mmc_get_clk(clk);
break;
+ case SCLK_UART0:
+ case SCLK_UART1:
+ case SCLK_UART2:
+ case SCLK_UART3:
+ case SCLK_UART4:
+ rate = rk3308_uart_get_clk(clk);
+ break;
case SCLK_I2C0:
case SCLK_I2C1:
case SCLK_I2C2: