| // SPDX-License-Identifier: GPL-2.0+ |
| * Common functions for OMAP4/5 based boards |
| * Texas Instruments, <www.ti.com> |
| * Aneesh V <aneesh@ti.com> |
| * Steve Sakoman <steve@sakoman.com> |
| #include <asm/global_data.h> |
| * Without LPAE short descriptors are used |
| * The last 2 bits set to 0b10 |
| * With LPAE cache configuration happens via MAIR0 register |
| * AttrIndx value is 0x3 for picking byte3 for MAIR0 which has 0xFF. |
| * 0xFF maps to Cache writeback with Read and Write Allocate set |
| * The bits[1:0] should have the value 0b01 for the first level |
| #define ARMV7_DCACHE_POLICY DCACHE_WRITEALLOC |
| #define ARMV7_DCACHE_POLICY DCACHE_WRITEBACK & ~TTB_SECT_XN_MASK |
| /* Enable I cache if not enabled */ |
| void dram_bank_mmu_setup(int bank) |
| struct bd_info *bd = gd->bd; |
| u32 start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT; |
| u32 size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT; |
| debug("%s: bank: %d\n", __func__, bank); |
| for (i = start; i < end; i++) |
| set_section_dcache(i, ARMV7_DCACHE_POLICY); |