| // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| /* |
| * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. |
| */ |
| |
| #include "rockchip-u-boot.dtsi" |
| |
| / { |
| dmc { |
| compatible = "rockchip,rk3588-dmc"; |
| bootph-all; |
| status = "okay"; |
| }; |
| |
| pmu1_grf: syscon@fd58a000 { |
| bootph-all; |
| compatible = "rockchip,rk3588-pmu1-grf", "syscon"; |
| reg = <0x0 0xfd58a000 0x0 0x2000>; |
| }; |
| |
| sdmmc: mmc@fe2c0000 { |
| compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc"; |
| reg = <0x0 0xfe2c0000 0x0 0x4000>; |
| interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>; |
| clocks = <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>, |
| <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>; |
| clock-names = "ciu-drive", "ciu-sample", "biu", "ciu"; |
| fifo-depth = <0x100>; |
| max-frequency = <200000000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &xin24m { |
| bootph-all; |
| status = "okay"; |
| }; |
| |
| &cru { |
| bootph-pre-ram; |
| status = "okay"; |
| }; |
| |
| &sys_grf { |
| bootph-pre-ram; |
| status = "okay"; |
| }; |
| |
| &uart2 { |
| clock-frequency = <24000000>; |
| bootph-pre-ram; |
| status = "okay"; |
| }; |
| |
| &ioc { |
| bootph-pre-ram; |
| }; |