| commit | 1f198594a967d44eb02ab6dec5daf8fa8a50364c | [log] [tgz] |
|---|---|---|
| author | Svyatoslav Ryhel <clamor95@gmail.com> | Fri Dec 13 16:53:18 2024 +0200 |
| committer | Tom Rini <trini@konsulko.com> | Mon Dec 16 17:07:39 2024 -0600 |
| tree | d1cb1e3b615410e9c01a2d42316490f9c7802a8a | |
| parent | e52b263b87c57202d8f42ccfc84fe036df22c789 [diff] |
driver: clk: tegra: partially support PLL clocks Return PLL id into struct clk if PLL is parsed from device tree instead of throwing an error. Allow requesting PLL clock rate via get_rate op. Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>