tree d1cb1e3b615410e9c01a2d42316490f9c7802a8a
parent e52b263b87c57202d8f42ccfc84fe036df22c789
author Svyatoslav Ryhel <clamor95@gmail.com> 1734101598 +0200
committer Tom Rini <trini@konsulko.com> 1734390459 -0600

driver: clk: tegra: partially support PLL clocks

Return PLL id into struct clk if PLL is parsed from device
tree instead of throwing an error. Allow requesting PLL
clock rate via get_rate op.

Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>