include/configs/t4qds.h - filogic/uboot - Gitiles

 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2011-2012 Freescale Semiconductor, Inc.
  */

 /*
  * Corenet DS style board configuration file
  */
 #ifndef __T4QDS_H
 #define __T4QDS_H

 /* High Level Configuration Options */
 #define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */

 #ifndef CONFIG_RESET_VECTOR_ADDRESS
 #define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
 #endif

 #define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
 #define CONFIG_SYS_NUM_CPC		CONFIG_SYS_NUM_DDR_CTLRS
 #define CONFIG_PCIE1			/* PCIE controller 1 */
 #define CONFIG_PCIE2			/* PCIE controller 2 */
 #define CONFIG_PCIE3			/* PCIE controller 3 */
 #define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
 #define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */

 #define CONFIG_SYS_SRIO
 #define CONFIG_SRIO1			/* SRIO port 1 */
 #define CONFIG_SRIO2			/* SRIO port 2 */

 #define CONFIG_ENV_OVERWRITE

 /*
  * These can be toggled for performance analysis, otherwise use default.
  */
 #define CONFIG_SYS_CACHE_STASHING
 #define CONFIG_BTB			/* toggle branch predition */
 #ifdef CONFIG_DDR_ECC
 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 #define CONFIG_MEM_INIT_VALUE		0xdeadbeef
 #endif

 #define CONFIG_ENABLE_36BIT_PHYS

 #define CONFIG_ADDR_MAP
 #define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */

 #define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x00400000

 /*
  *  Config the L3 Cache as L3 SRAM
  */
 #define CONFIG_SYS_INIT_L3_ADDR		0xFFFC0000
 #define CONFIG_SYS_L3_SIZE		(512 << 10)
 #define CONFIG_SPL_GD_ADDR		(CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 #ifdef CONFIG_RAMBOOT_PBL
 #define CONFIG_ENV_ADDR			(CONFIG_SPL_GD_ADDR + 4 * 1024)
 #endif
 #define CONFIG_SPL_RELOC_MALLOC_ADDR	(CONFIG_SPL_GD_ADDR + 12 * 1024)
 #define CONFIG_SPL_RELOC_MALLOC_SIZE	(50 << 10)
 #define CONFIG_SPL_RELOC_STACK		(CONFIG_SPL_GD_ADDR + 64 * 1024)

 #define CONFIG_SYS_DCSRBAR		0xf0000000
 #define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull

 /*
  * DDR Setup
  */
 #define CONFIG_VERY_BIG_RAM
 #define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
 #define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

 #define CONFIG_DIMM_SLOTS_PER_CTLR	2
 #define CONFIG_CHIP_SELECTS_PER_CTRL	4
 #define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE

 #define CONFIG_DDR_SPD

 /*
  * IFC Definitions
  */
 #define CONFIG_SYS_FLASH_BASE	0xe0000000
 #define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)

 #ifdef CONFIG_SPL_BUILD
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SPL_TEXT_BASE
 #else
 #define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */
 #endif

 #define CONFIG_MISC_INIT_R

 #define CONFIG_HWCONFIG

 /* define to use L1 as initial stack */
 #define CONFIG_L1_INIT_RAM
 #define CONFIG_SYS_INIT_RAM_LOCK
 #define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe03c000
 /* The assembler doesn't like typecast */
 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 #define CONFIG_SYS_INIT_RAM_SIZE		0x00004000

 #define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
 					GENERATED_GBL_DATA_SIZE)
 #define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

 #define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
 #define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)

 /* Serial Port - controlled on board with jumper J8
  * open - index 2
  * shorted - index 1
  */
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE	1
 #define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)

 #define CONFIG_SYS_BAUDRATE_TABLE	\
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

 #define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
 #define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
 #define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
 #define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)

 /* I2C */
 #define CONFIG_SYS_I2C
 #define CONFIG_SYS_I2C_FSL
 #define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C_OFFSET	0x118000
 #define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
 #define CONFIG_SYS_FSL_I2C2_OFFSET	0x118100

 /*
  * RapidIO
  */
 #define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */

 #define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
 #define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
 #define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */

 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */

 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 #define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
 #define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
 #define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
 #define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
 #define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

 /* controller 2, Slot 2, tgtid 2, Base address 201000 */
 #define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
 #define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
 #define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE2_IO_VIRT	0xf8010000
 #define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE2_IO_PHYS	0xff8010000ull
 #define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */

 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 #define CONFIG_SYS_PCIE3_MEM_VIRT	0xc0000000
 #define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE3_MEM_PHYS	0xc40000000ull
 #define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE3_IO_VIRT	0xf8020000
 #define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE3_IO_PHYS	0xff8020000ull
 #define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */

 /* controller 4, Base address 203000 */
 #define CONFIG_SYS_PCIE4_MEM_BUS	0xe0000000
 #define CONFIG_SYS_PCIE4_MEM_PHYS	0xc60000000ull
 #define CONFIG_SYS_PCIE4_MEM_SIZE	0x20000000	/* 512M */
 #define CONFIG_SYS_PCIE4_IO_BUS		0x00000000
 #define CONFIG_SYS_PCIE4_IO_PHYS	0xff8030000ull
 #define CONFIG_SYS_PCIE4_IO_SIZE	0x00010000	/* 64k */

 #ifdef CONFIG_PCI
 #define CONFIG_PCI_INDIRECT_BRIDGE

 #define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #endif	/* CONFIG_PCI */

 /* SATA */
 #ifdef CONFIG_FSL_SATA_V2
 #define CONFIG_SYS_SATA_MAX_DEVICE	2
 #define CONFIG_SATA1
 #define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
 #define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
 #define CONFIG_SATA2
 #define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
 #define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA

 #define CONFIG_LBA48
 #endif

 #ifdef CONFIG_FMAN_ENET
 #define CONFIG_MII		/* MII PHY management */
 #define CONFIG_ETHPRIME		"FM1@DTSEC1"
 #endif

 /*
  * Environment
  */
 #define CONFIG_LOADS_ECHO		/* echo on for serial download */
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */

 /*
  * Command line configuration.
  */

 /*
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
 #define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
 #define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

 #ifdef CONFIG_CMD_KGDB
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #endif

 /*
  * Environment Configuration
  */
 #define CONFIG_ROOTPATH		"/opt/nfsroot"
 #define CONFIG_BOOTFILE		"uImage"
 #define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/

 /* default location for tftp and bootm */
 #define CONFIG_LOADADDR		1000000

 #define CONFIG_HVBOOT				\
  "setenv bootargs config-addr=0x60000000; "	\
  "bootm 0x01000000 - 0x00f00000"

 #endif	/* __CONFIG_H */
	/* SPDX-License-Identifier: GPL-2.0+ */
	/*
	* Copyright 2011-2012 Freescale Semiconductor, Inc.
	*/

	/*
	* Corenet DS style board configuration file
	*/
	#ifndef __T4QDS_H
	#define __T4QDS_H

	/* High Level Configuration Options */
	#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */

	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	#endif

	#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
	#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
	#define CONFIG_PCIE1 /* PCIE controller 1 */
	#define CONFIG_PCIE2 /* PCIE controller 2 */
	#define CONFIG_PCIE3 /* PCIE controller 3 */
	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */

	#define CONFIG_SYS_SRIO
	#define CONFIG_SRIO1 /* SRIO port 1 */
	#define CONFIG_SRIO2 /* SRIO port 2 */

	#define CONFIG_ENV_OVERWRITE

	/*
	* These can be toggled for performance analysis, otherwise use default.
	*/
	#define CONFIG_SYS_CACHE_STASHING
	#define CONFIG_BTB /* toggle branch predition */
	#ifdef CONFIG_DDR_ECC
	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	#endif

	#define CONFIG_ENABLE_36BIT_PHYS

	#define CONFIG_ADDR_MAP
	#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */

	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
	#define CONFIG_SYS_MEMTEST_END 0x00400000

	/*
	* Config the L3 Cache as L3 SRAM
	*/
	#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
	#define CONFIG_SYS_L3_SIZE (512 << 10)
	#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
	#ifdef CONFIG_RAMBOOT_PBL
	#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
	#endif
	#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
	#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
	#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)

	#define CONFIG_SYS_DCSRBAR 0xf0000000
	#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull

	/*
	* DDR Setup
	*/
	#define CONFIG_VERY_BIG_RAM
	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE

	#define CONFIG_DIMM_SLOTS_PER_CTLR 2
	#define CONFIG_CHIP_SELECTS_PER_CTRL 4
	#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE

	#define CONFIG_DDR_SPD

	/*
	* IFC Definitions
	*/
	#define CONFIG_SYS_FLASH_BASE 0xe0000000
	#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull \| CONFIG_SYS_FLASH_BASE)

	#ifdef CONFIG_SPL_BUILD
	#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
	#else
	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
	#endif

	#define CONFIG_MISC_INIT_R

	#define CONFIG_HWCONFIG

	/* define to use L1 as initial stack */
	#define CONFIG_L1_INIT_RAM
	#define CONFIG_SYS_INIT_RAM_LOCK
	#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
	/* The assembler doesn't like typecast */
	#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) \| \
	CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000

	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
	GENERATED_GBL_DATA_SIZE)
	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET

	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)

	/* Serial Port - controlled on board with jumper J8
	* open - index 2
	* shorted - index 1
	*/
	#define CONFIG_SYS_NS16550_SERIAL
	#define CONFIG_SYS_NS16550_REG_SIZE 1
	#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)

	#define CONFIG_SYS_BAUDRATE_TABLE \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
	#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
	#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)

	/* I2C */
	#define CONFIG_SYS_I2C
	#define CONFIG_SYS_I2C_FSL
	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100

	/*
	* RapidIO
	*/
	#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
	#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
	#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */

	#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
	#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
	#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */

	/*
	* General PCI
	* Memory space is mapped 1-1, but I/O space must start from 0.
	*/

	/* controller 1, direct to uli, tgtid 3, Base address 20000 */
	#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
	#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
	#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */

	/* controller 2, Slot 2, tgtid 2, Base address 201000 */
	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
	#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
	#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
	#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */

	/* controller 3, Slot 1, tgtid 1, Base address 202000 */
	#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
	#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
	#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
	#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
	#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
	#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
	#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */

	/* controller 4, Base address 203000 */
	#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
	#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
	#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
	#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
	#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
	#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */

	#ifdef CONFIG_PCI
	#define CONFIG_PCI_INDIRECT_BRIDGE

	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	#endif /* CONFIG_PCI */

	/* SATA */
	#ifdef CONFIG_FSL_SATA_V2
	#define CONFIG_SYS_SATA_MAX_DEVICE 2
	#define CONFIG_SATA1
	#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
	#define CONFIG_SATA2
	#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA

	#define CONFIG_LBA48
	#endif

	#ifdef CONFIG_FMAN_ENET
	#define CONFIG_MII /* MII PHY management */
	#define CONFIG_ETHPRIME "FM1@DTSEC1"
	#endif

	/*
	* Environment
	*/
	#define CONFIG_LOADS_ECHO /* echo on for serial download */
	#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */

	/*
	* Command line configuration.
	*/

	/*
	* Miscellaneous configurable options
	*/
	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */

	/*
	* For booting Linux, the board info and command line data
	* have to be in the first 64 MB of memory, since this is
	* the maximum mapped by the Linux kernel during initialization.
	*/
	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */

	#ifdef CONFIG_CMD_KGDB
	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	#endif

	/*
	* Environment Configuration
	*/
	#define CONFIG_ROOTPATH "/opt/nfsroot"
	#define CONFIG_BOOTFILE "uImage"
	#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/

	/* default location for tftp and bootm */
	#define CONFIG_LOADADDR 1000000

	#define CONFIG_HVBOOT \
	"setenv bootargs config-addr=0x60000000; " \
	"bootm 0x01000000 - 0x00f00000"

	#endif /* __CONFIG_H */