| # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml# |
| $schema: http://devicetree.org/meta-schemas/core.yaml# |
| title: Rockchip MIPI DPHY with additional LVDS/TTL modes |
| - Heiko Stuebner <heiko@sntech.de> |
| - rockchip,rk3128-dsi-dphy |
| - rockchip,rk3368-dsi-dphy |
| - rockchip,rk3568-dsi-dphy |
| - rockchip,rv1126-dsi-dphy |
| - description: PLL reference clock |
| - description: Module clock |
| description: phandle to the associated power domain |
| - description: exclusive PHY reset line |
| additionalProperties: false |
| compatible = "rockchip,px30-dsi-dphy"; |
| reg = <0xff2e0000 0x10000>; |
| clocks = <&pmucru 13>, <&cru 12>; |
| clock-names = "ref", "pclk"; |