| * MCR3000 Device Tree Source |
| * Copyright 2017 CS Systemes d'Information |
| * SPDX-License-Identifier: GPL-2.0+ |
| compatible = "simple-bus"; |
| ranges = <0 0xff000000 0x4000>; |
| reg = <0xff000000 0x00000200>; |
| compatible = "fsl,pq1-wdt"; |
| compatible = "fsl,mpc8xx-spi"; |
| compatible = "s3k,mcr3000-localbus", "fsl,pq1-localbus", "simple-bus"; |
| reg = <0xff000100 0x40>; // ORx and BRx register |
| ranges = <0 0 0x04000000 0x04000000 // BOOT |
| 1 0 0x00000000 0x04000000 // SDRAM |
| 2 0 0x08000000 0x04000000 // RAMDP |
| 3 0 0x0C000000 0x04000000 // NAND |
| 4 0 0x10000000 0x04000000 // Periphs |
| 5 0 0x14000000 0x04000000 // FPGA |
| 6 0 0x18000000 0x04000000 // mezzanine |
| 7 0 0x1c000000 0x04000000>; // DSP |
| csspi: gpio-controller@2 { |
| compatible = "s3k,mcr3000-cpld-csspi"; |
| compatible = "fsl,pq1-smc"; |
| compatible = "fsl,pq1-fec1"; |