| commit | 0f106ccc57be4fd6e41478a9f7d8ed592700782f | [log] [tgz] |
|---|---|---|
| author | David Wu <david.wu@rock-chips.com> | Wed Sep 20 14:28:18 2017 +0800 |
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | Sun Oct 01 00:33:29 2017 +0200 |
| tree | 1aca6576b715876b47853f4aab24c0f353464676 | |
| parent | f8d5bc7517c14e4f835df9e5e0b575667dc6fd48 [diff] |
rockchip: clk: Add rv1108 SARADC clock support The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). SARADC integer divider control register is 10-bits width. Signed-off-by: David Wu <david.wu@rock-chips.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>