tree 1aca6576b715876b47853f4aab24c0f353464676
parent f8d5bc7517c14e4f835df9e5e0b575667dc6fd48
author David Wu <david.wu@rock-chips.com> 1505888898 +0800
committer Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 1506810809 +0200

rockchip: clk: Add rv1108 SARADC clock support

The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.

Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>