| Support AXI (Advanced eXtensible Interface) busses, a on-chip |
| interconnect specification for managing functional blocks in SoC |
| designs, which is also often used in designs involving FPGAs (e.g. |
| communication with IP cores in Xilinx FPGAs). |
| These types of busses expose a virtual address space that can be |
| accessed using different address widths (8, 16, and 32 are supported |
| Other similar bus architectures may be compatible as well. |
| bool "Enable IHS AXI driver" |
| Support for gdsys Integrated Hardware Systems Advanced eXtensible |
| Interface (IHS AXI) bus on a gdsys IHS FPGA used to communicate with |
| IP cores in the FPGA (e.g. video transmitter cores). |
| bool "Enable AXI sandbox driver" |
| Support AXI (Advanced eXtensible Interface) emulation for the sandbox |