board/freescale/t208xqds/t2081_spi_rcw.cfg - filogic/uboot - Gitiles

 #PBL preamble and RCW header
 aa55aa55 010e0100
 #Default SerDes Protocol: 0x6C
 #Core/DDR: 1533Mhz/2133MT/s
 12100017 15000000 00000000 00000000
 6c000002 00008000 58104000 c1000000
 00000000 00000000 00000000 000307fc
 00000000 00000000 00000000 00000004
	#PBL preamble and RCW header
	aa55aa55 010e0100
	#Default SerDes Protocol: 0x6C
	#Core/DDR: 1533Mhz/2133MT/s
	12100017 15000000 00000000 00000000
	6c000002 00008000 58104000 c1000000
	00000000 00000000 00000000 000307fc
	00000000 00000000 00000000 00000004