| // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| * P2020RDB-PC Device Tree Source |
| * Copyright 2013 - 2015 Freescale Semiconductor Inc. |
| model = "fsl,P2020RDB-PC"; |
| compatible = "fsl,P2020RDB-PC"; |
| interrupt-parent = <&mpic>; |
| reg = <0 0xffe05000 0 0x1000>; |
| ranges = <0x0 0x0 0xffe00000 0x100000>; |
| reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */ |
| reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ |
| ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ |
| 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ |
| reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ |
| ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ |
| 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ |
| /include/ "p2020rdb-pc.dtsi" |
| /include/ "p2020-post.dtsi" |
| compatible = "jedec,spi-nor"; |
| spi-max-frequency = <10000000>; /* input clock */ |