MIPS: mips32/cache.S: use v1 register for indirect function calls
Synchronize the code with mips64/cache.S, in order to
allow further unifications.
Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
diff --git a/arch/mips/cpu/mips32/cache.S b/arch/mips/cpu/mips32/cache.S
index d3f156e..12f656c 100644
--- a/arch/mips/cpu/mips32/cache.S
+++ b/arch/mips/cpu/mips32/cache.S
@@ -156,16 +156,16 @@
*/
move a1, t2
move a2, t8
- PTR_LA t7, mips_init_icache
- jalr t7
+ PTR_LA v1, mips_init_icache
+ jalr v1
/*
* then initialize D-cache.
*/
move a1, t3
move a2, t8
- PTR_LA t7, mips_init_dcache
- jalr t7
+ PTR_LA v1, mips_init_dcache
+ jalr v1
jr RA
END(mips_cache_reset)