| commit | 5b4f4ffad3a92a3707cf16fbb9c26cf094e6d312 | [log] [tgz] |
|---|---|---|
| author | Gabor Juhos <juhosg@openwrt.org> | Thu Jun 13 12:59:35 2013 +0200 |
| committer | Tom Rini <trini@ti.com> | Wed Jul 24 09:51:07 2013 -0400 |
| tree | 0bc3e953a2bf45c34e985dd7a8714a674c3ce440 | |
| parent | 187fe8119da9ee96660a32c721d611300bd01721 [diff] |
MIPS: mips32/cache.S: store cache line size in t8 register Synchronize the code with mips64/cache.S, in order to allow further unifications. Signed-off-by: Gabor Juhos <juhosg@openwrt.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>