// SPDX-License-Identifier: GPL-2.0+ | |
/* | |
* Copyright 2019 NXP | |
* Copyright 2022 Linaro | |
*/ | |
#include "imx8mp-u-boot.dtsi" | |
/ { | |
wdt-reboot { | |
compatible = "wdt-reboot"; | |
wdt = <&wdog1>; | |
u-boot,dm-spl; | |
}; | |
firmware { | |
optee { | |
compatible = "linaro,optee-tz"; | |
method = "smc"; | |
}; | |
}; | |
}; | |
&iomuxc { | |
u-boot,dm-spl; | |
}; | |
®_usdhc2_vmmc { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_uart2 { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_uart3 { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_usdhc2_gpio { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_usdhc2 { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_usdhc3 { | |
u-boot,dm-spl; | |
}; | |
&gpio1 { | |
u-boot,dm-spl; | |
}; | |
&gpio2 { | |
u-boot,dm-spl; | |
}; | |
&gpio3 { | |
u-boot,dm-spl; | |
}; | |
&gpio4 { | |
u-boot,dm-spl; | |
}; | |
&gpio5 { | |
u-boot,dm-spl; | |
}; | |
&uart2 { | |
u-boot,dm-spl; | |
}; | |
&uart3 { | |
u-boot,dm-spl; | |
}; | |
&i2c1 { | |
u-boot,dm-spl; | |
}; | |
&i2c2 { | |
u-boot,dm-spl; | |
}; | |
&i2c3 { | |
u-boot,dm-spl; | |
}; | |
&wdog1 { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_wdog { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_i2c1 { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_i2c1_gpio { | |
u-boot,dm-spl; | |
}; | |
&pinctrl_pmic { | |
u-boot,dm-spl; | |
}; | |
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25} { | |
u-boot,dm-spl; | |
}; | |
&{/soc@0/bus@30800000/i2c@30a20000/pca9450@25/regulators} { | |
u-boot,dm-spl; | |
}; | |
&usdhc1 { | |
u-boot,dm-spl; | |
assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; | |
assigned-clock-rates = <400000000>; | |
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; | |
}; | |
&usdhc2 { | |
u-boot,dm-spl; | |
sd-uhs-sdr104; | |
sd-uhs-ddr50; | |
assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; | |
assigned-clock-rates = <400000000>; | |
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; | |
}; | |
&usdhc3 { | |
u-boot,dm-spl; | |
mmc-hs400-1_8v; | |
mmc-hs400-enhanced-strobe; | |
assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; | |
assigned-clock-rates = <400000000>; | |
assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_400M>; | |
}; | |
&binman { | |
itb { | |
fit { | |
images { | |
fip { | |
description = "Trusted Firmware FIP"; | |
type = "firmware"; | |
arch = "arm64"; | |
compression = "none"; | |
load = <0x40310000>; | |
fip_blob: blob-ext{ | |
filename = "fip.bin"; | |
}; | |
}; | |
}; | |
}; | |
}; | |
}; | |
&binman_configuration { | |
loadables = "atf", "fip"; | |
}; |