| // SPDX-License-Identifier: GPL-2.0+ |
| * Clock drivers for Qualcomm IPQ40xx |
| * Copyright (c) 2019 Sartura Ltd. |
| * Author: Robert Marko <robert.marko@sartura.hr> |
| ulong msm_set_rate(struct clk *clk, ulong rate) |
| /* This clock is already initialized by SBL1 */ |
| static int msm_clk_probe(struct udevice *dev) |
| struct msm_clk_priv *priv = dev_get_priv(dev); |
| priv->base = devfdt_get_addr(dev); |
| if (priv->base == FDT_ADDR_T_NONE) |
| static ulong msm_clk_set_rate(struct clk *clk, ulong rate) |
| return msm_set_rate(clk, rate); |
| static struct clk_ops msm_clk_ops = { |
| .set_rate = msm_clk_set_rate, |
| static const struct udevice_id msm_clk_ids[] = { |
| { .compatible = "qcom,gcc-ipq4019" }, |
| U_BOOT_DRIVER(clk_msm) = { |
| .priv_auto_alloc_size = sizeof(struct msm_clk_priv), |