| // SPDX-License-Identifier: GPL-2.0+ | |
| /* | |
| * (C) Copyright 2021 Rockchip Electronics Co., Ltd | |
| * (C) Copyright 2023 Akash Gajjar <gajjar04akash@gmail.com> | |
| */ | |
| #include "rk356x-u-boot.dtsi" | |
| / { | |
| chosen { | |
| stdout-path = &uart2; | |
| }; | |
| }; | |
| &pcie3x2 { | |
| pinctrl-0 = <&pcie3x2_reset_h>; | |
| }; | |
| &pinctrl { | |
| pcie { | |
| pcie3x2_reset_h: pcie3x2-reset-h { | |
| rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>; | |
| }; | |
| }; | |
| }; | |
| &sdhci { | |
| cap-mmc-highspeed; | |
| mmc-ddr-1_8v; | |
| mmc-hs200-1_8v; | |
| mmc-hs400-1_8v; | |
| mmc-hs400-enhanced-strobe; | |
| }; | |
| &sfc { | |
| bootph-pre-ram; | |
| u-boot,spl-sfc-no-dma; | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| status = "okay"; | |
| flash@0 { | |
| bootph-pre-ram; | |
| compatible = "jedec,spi-nor"; | |
| reg = <0>; | |
| spi-max-frequency = <24000000>; | |
| spi-rx-bus-width = <4>; | |
| spi-tx-bus-width = <1>; | |
| }; | |
| }; | |
| &uart2 { | |
| clock-frequency = <24000000>; | |
| bootph-all; | |
| status = "okay"; | |
| }; |