developer | 004e50c | 2023-06-29 20:33:22 +0800 | [diff] [blame] | 1 | From 78bc83a6a4dc69f135c6a32756e8acb96c64b1bf Mon Sep 17 00:00:00 2001 |
| 2 | From: Peter Chiu <chui-hao.chiu@mediatek.com> |
| 3 | Date: Tue, 13 Jun 2023 09:04:43 +0800 |
| 4 | Subject: [PATCH] wifi: mt76: mt7996: adjust wfdma setting to enhance |
| 5 | throughput |
| 6 | |
| 7 | 1. Set band 1 traffic to pcie1. |
| 8 | 2. Refactor dma prefetch and enlarge txd prefetch size. |
| 9 | 3. Update pdma setting. |
| 10 | |
| 11 | Signed-off-by: Peter Chiu <chui-hao.chiu@mediatek.com> |
| 12 | --- |
| 13 | mt7996/dma.c | 57 ++++++++++++++++++++++++++++++++++++++------------- |
| 14 | mt7996/regs.h | 9 ++++++++ |
| 15 | 2 files changed, 52 insertions(+), 14 deletions(-) |
| 16 | |
| 17 | diff --git a/mt7996/dma.c b/mt7996/dma.c |
| 18 | index f01cea5e..bb390517 100644 |
| 19 | --- a/mt7996/dma.c |
| 20 | +++ b/mt7996/dma.c |
| 21 | @@ -56,22 +56,34 @@ static void mt7996_dma_config(struct mt7996_dev *dev) |
| 22 | MCUQ_CONFIG(MT_MCUQ_FWDL, WFDMA0, MT_INT_TX_DONE_FWDL, MT7996_TXQ_FWDL); |
| 23 | } |
| 24 | |
| 25 | +static u32 __mt7996_dma_prefetch_base(u16 *base, u8 depth) |
| 26 | +{ |
| 27 | + u32 ret = *base << 16 | depth; |
| 28 | + |
| 29 | + *base = *base + (depth << 4); |
| 30 | + |
| 31 | + return ret; |
| 32 | +} |
| 33 | + |
| 34 | static void __mt7996_dma_prefetch(struct mt7996_dev *dev, u32 ofs) |
| 35 | { |
| 36 | -#define PREFETCH(_base, _depth) ((_base) << 16 | (_depth)) |
| 37 | + u16 base = 0; |
| 38 | + |
| 39 | +#define PREFETCH(_depth) (__mt7996_dma_prefetch_base(&base, (_depth))) |
| 40 | /* prefetch SRAM wrapping boundary for tx/rx ring. */ |
| 41 | - mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x0, 0x2)); |
| 42 | - mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x20, 0x2)); |
| 43 | - mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x40, 0x4)); |
| 44 | - mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x80, 0x4)); |
| 45 | - mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0xc0, 0x2)); |
| 46 | - mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0xe0, 0x4)); |
| 47 | - mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x120, 0x2)); |
| 48 | - mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x140, 0x2)); |
| 49 | - mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x160, 0x2)); |
| 50 | - mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x180, 0x2)); |
| 51 | - mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x1a0, 0x10)); |
| 52 | - mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x2a0, 0x10)); |
| 53 | + mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_FWDL) + ofs, PREFETCH(0x2)); |
| 54 | + mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WM) + ofs, PREFETCH(0x2)); |
| 55 | + mt76_wr(dev, MT_TXQ_EXT_CTRL(0) + ofs, PREFETCH(0x8)); |
| 56 | + mt76_wr(dev, MT_TXQ_EXT_CTRL(1) + ofs, PREFETCH(0x8)); |
| 57 | + mt76_wr(dev, MT_MCUQ_EXT_CTRL(MT_MCUQ_WA) + ofs, PREFETCH(0x2)); |
| 58 | + mt76_wr(dev, MT_TXQ_EXT_CTRL(2) + ofs, PREFETCH(0x8)); |
| 59 | + mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU) + ofs, PREFETCH(0x2)); |
| 60 | + mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MCU_WA) + ofs, PREFETCH(0x2)); |
| 61 | + mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN_WA) + ofs, PREFETCH(0x2)); |
| 62 | + mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2_WA) + ofs, PREFETCH(0x2)); |
| 63 | + mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_MAIN) + ofs, PREFETCH(0x10)); |
| 64 | + mt76_wr(dev, MT_RXQ_BAND1_CTRL(MT_RXQ_BAND2) + ofs, PREFETCH(0x10)); |
| 65 | +#undef PREFETCH |
| 66 | |
| 67 | mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + ofs, WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE); |
| 68 | } |
| 69 | @@ -223,6 +235,12 @@ static int mt7996_dma_enable(struct mt7996_dev *dev, bool reset) |
| 70 | mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1, |
| 71 | WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE); |
| 72 | |
| 73 | + /* WFDMA rx threshold */ |
| 74 | + mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_45_TH, 0xc000c); |
| 75 | + mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_67_TH, 0x10008); |
| 76 | + mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_89_TH, 0x10008); |
| 77 | + mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_RRO_TH, 0x20); |
| 78 | + |
| 79 | if (dev->hif2) { |
| 80 | /* GLO_CFG_EXT0 */ |
| 81 | mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs, |
| 82 | @@ -234,7 +252,18 @@ static int mt7996_dma_enable(struct mt7996_dev *dev, bool reset) |
| 83 | WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE); |
| 84 | |
| 85 | mt76_set(dev, MT_WFDMA_HOST_CONFIG, |
| 86 | - MT_WFDMA_HOST_CONFIG_PDMA_BAND); |
| 87 | + MT_WFDMA_HOST_CONFIG_PDMA_BAND | |
| 88 | + MT_WFDMA_HOST_CONFIG_BAND2_PCIE1); |
| 89 | + |
| 90 | + /* AXI read outstanding number */ |
| 91 | + mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL, |
| 92 | + MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK, 0x14); |
| 93 | + |
| 94 | + /* WFDMA rx threshold */ |
| 95 | + mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_45_TH + hif1_ofs, 0xc000c); |
| 96 | + mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_67_TH + hif1_ofs, 0x10008); |
| 97 | + mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_89_TH + hif1_ofs, 0x10008); |
| 98 | + mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_RRO_TH + hif1_ofs, 0x20); |
| 99 | } |
| 100 | |
| 101 | if (dev->hif2) { |
| 102 | diff --git a/mt7996/regs.h b/mt7996/regs.h |
| 103 | index 3a5914c4..5917ba1a 100644 |
| 104 | --- a/mt7996/regs.h |
| 105 | +++ b/mt7996/regs.h |
| 106 | @@ -333,6 +333,11 @@ enum base_rev { |
| 107 | #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO BIT(27) |
| 108 | #define MT_WFDMA0_GLO_CFG_OMIT_RX_INFO_PFET2 BIT(21) |
| 109 | |
| 110 | +#define MT_WFDMA0_PAUSE_RX_Q_45_TH MT_WFDMA0(0x268) |
| 111 | +#define MT_WFDMA0_PAUSE_RX_Q_67_TH MT_WFDMA0(0x26c) |
| 112 | +#define MT_WFDMA0_PAUSE_RX_Q_89_TH MT_WFDMA0(0x270) |
| 113 | +#define MT_WFDMA0_PAUSE_RX_Q_RRO_TH MT_WFDMA0(0x27c) |
| 114 | + |
| 115 | #define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) |
| 116 | #define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD BIT(18) |
| 117 | #define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE BIT(14) |
| 118 | @@ -355,10 +360,14 @@ enum base_rev { |
| 119 | |
| 120 | #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) |
| 121 | #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) |
| 122 | +#define MT_WFDMA_HOST_CONFIG_BAND2_PCIE1 BIT(22) |
| 123 | |
| 124 | #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44) |
| 125 | #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0) |
| 126 | |
| 127 | +#define MT_WFDMA_AXI_R2A_CTRL MT_WFDMA_EXT_CSR(0x500) |
| 128 | +#define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK GENMASK(4, 0) |
| 129 | + |
| 130 | #define MT_PCIE_RECOG_ID 0xd7090 |
| 131 | #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) |
| 132 | #define MT_PCIE_RECOG_ID_SEM BIT(31) |
| 133 | -- |
| 134 | 2.18.0 |
| 135 | |