developer | f10a898 | 2022-10-17 12:01:44 +0800 | [diff] [blame^] | 1 | From 5f8c12ffa661e3707790f59827a45ff4102f2886 Mon Sep 17 00:00:00 2001 |
| 2 | From: Zhanyong Wang <zhanyong.wang@mediatek.com> |
| 3 | Date: Mon, 15 Aug 2022 14:13:50 +0800 |
| 4 | Subject: [PATCH] xHCI: change compliance mode de-emphasis default as gen1 |
| 5 | |
| 6 | Port0 is using Gen2 Phy for 10GHz, and Port0 is running |
| 7 | on 5GHz actually. hence to change compliance mode de- |
| 8 | emphasis default as Gen1. |
| 9 | |
| 10 | Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com> |
| 11 | --- |
| 12 | drivers/usb/host/xhci-mtk.c | 15 +++++++++++++++ |
| 13 | 1 file changed, 15 insertions(+) |
| 14 | |
| 15 | diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c |
| 16 | index 2a4b73a658f9..b1201fb65fd6 100644 |
| 17 | --- a/drivers/usb/host/xhci-mtk.c |
| 18 | +++ b/drivers/usb/host/xhci-mtk.c |
| 19 | @@ -24,6 +24,11 @@ |
| 20 | #include "xhci-mtk.h" |
| 21 | #include "xhci-mtk-test.h" |
| 22 | |
| 23 | +/* COMPLIANCE_CP5_CP7_TXDEEMPH_10G register */ |
| 24 | +#define COMPLIANCE_CP5_CP7_TXDEEMPH_10G 0x2428 |
| 25 | +#define CP5_CP7_TXDEEMPH_10G GENMASK(17, 0) |
| 26 | +#define CP5_CP7_TXDEEMPH_10G_VAL(val) ((val) & 0x03FFFF) |
| 27 | + |
| 28 | /* ip_pw_ctrl0 register */ |
| 29 | #define CTRL0_IP_SW_RST BIT(0) |
| 30 | |
| 31 | @@ -415,6 +420,7 @@ static int xhci_mtk_setup(struct usb_hcd *hcd) |
| 32 | { |
| 33 | struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd); |
| 34 | int ret; |
| 35 | + u32 val; |
| 36 | |
| 37 | if (usb_hcd_is_primary_hcd(hcd)) { |
| 38 | ret = xhci_mtk_ssusb_config(mtk); |
| 39 | @@ -432,6 +438,15 @@ static int xhci_mtk_setup(struct usb_hcd *hcd) |
| 40 | return ret; |
| 41 | } |
| 42 | |
| 43 | + /* change COMPLIANCE_CP5_CP7_TXDEEMPH_10G as Gen1 instead Gen2 */ |
| 44 | + if (hcd->rsrc_start == 0x11190000ULL) { |
| 45 | + val = readl(mtk->hcd->regs + COMPLIANCE_CP5_CP7_TXDEEMPH_10G); |
| 46 | + val &= ~CP5_CP7_TXDEEMPH_10G; |
| 47 | + val |= 0x00001; |
| 48 | + val = CP5_CP7_TXDEEMPH_10G_VAL(val); |
| 49 | + writel(val, mtk->hcd->regs + COMPLIANCE_CP5_CP7_TXDEEMPH_10G); |
| 50 | + } |
| 51 | + |
| 52 | return ret; |
| 53 | } |
| 54 | |
| 55 | -- |
| 56 | 2.18.0 |
| 57 | |