developer | 43a264f | 2024-03-26 14:09:54 +0800 | [diff] [blame] | 1 | From f513775361c7aae98ca2f816edb62b1744350325 Mon Sep 17 00:00:00 2001 |
| 2 | From: Rex Lu <rex.lu@mediatek.com> |
| 3 | Date: Thu, 1 Feb 2024 10:32:42 +0800 |
| 4 | Subject: [PATCH 2022/2032] mtk: wifi: mt76: mt7996: eagle support extra |
| 5 | option_type |
| 6 | |
| 7 | 1. eagle + mt7988d option_type 2 support |
| 8 | 2. eagle single pcie support |
| 9 | |
| 10 | Signed-off-by: Rex Lu <rex.lu@mediatek.com> |
| 11 | |
| 12 | 1. adjust pcie outstanding value by pcie speed. not no longer by option_type. |
| 13 | |
| 14 | Signed-off-by: Rex Lu <rex.lu@mediatek.com> |
| 15 | --- |
| 16 | mt7996/dma.c | 51 +++++++++++++++++++++++++++++++++---- |
| 17 | mt7996/init.c | 67 ++++++++++++++++++++++++++++++++++++++----------- |
| 18 | mt7996/main.c | 15 +++++++++-- |
| 19 | mt7996/mt7996.h | 5 ++++ |
| 20 | mt7996/pci.c | 2 +- |
| 21 | mt7996/regs.h | 5 ++++ |
| 22 | 6 files changed, 123 insertions(+), 22 deletions(-) |
| 23 | |
| 24 | diff --git a/mt7996/dma.c b/mt7996/dma.c |
| 25 | index c23b0d65..3dc0e8a1 100644 |
| 26 | --- a/mt7996/dma.c |
| 27 | +++ b/mt7996/dma.c |
| 28 | @@ -12,12 +12,20 @@ int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx, int n_desc, |
| 29 | { |
| 30 | struct mt7996_dev *dev = phy->dev; |
| 31 | u32 flags = 0; |
| 32 | + int i; |
| 33 | + |
| 34 | + if (phy->mt76->band_idx == MT_BAND1 && !dev->hif2 && is_mt7996(&dev->mt76)) { |
| 35 | + phy->mt76->q_tx[0] = phy->mt76->dev->phys[MT_BAND0]->q_tx[0]; |
| 36 | + for (i = 1; i <= MT_TXQ_PSD; i++) |
| 37 | + phy->mt76->q_tx[i] = phy->mt76->q_tx[0]; |
| 38 | + return 0; |
| 39 | + } |
| 40 | |
| 41 | if (mtk_wed_device_active(wed)) { |
| 42 | ring_base += MT_TXQ_ID(0) * MT_RING_SIZE; |
| 43 | idx -= MT_TXQ_ID(0); |
| 44 | |
| 45 | - if (phy->mt76->band_idx == MT_BAND2) |
| 46 | + if (wed == &dev->mt76.mmio.wed_hif2) |
| 47 | flags = MT_WED_Q_TX(0); |
| 48 | else |
| 49 | flags = MT_WED_Q_TX(idx); |
| 50 | @@ -102,8 +110,20 @@ static void mt7996_dma_config(struct mt7996_dev *dev) |
| 51 | /* data tx queue */ |
| 52 | TXQ_CONFIG(0, WFDMA0, MT_INT_TX_DONE_BAND0, MT7996_TXQ_BAND0); |
| 53 | if (is_mt7996(&dev->mt76)) { |
| 54 | - TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1); |
| 55 | - TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2); |
| 56 | + if (dev->hif2) { |
| 57 | + if (dev->option_type == 2) { |
| 58 | + /* bn1:ring21 bn2:ring19 */ |
| 59 | + TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2); |
| 60 | + TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1); |
| 61 | + } else { |
| 62 | + /* default bn1:ring19 bn2:ring21 */ |
| 63 | + TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1); |
| 64 | + TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND2, MT7996_TXQ_BAND2); |
| 65 | + } |
| 66 | + } else { |
| 67 | + /* single pcie bn0/1:ring18 bn2:ring19 */ |
| 68 | + TXQ_CONFIG(2, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1); |
| 69 | + } |
| 70 | } else { |
| 71 | TXQ_CONFIG(1, WFDMA0, MT_INT_TX_DONE_BAND1, MT7996_TXQ_BAND1); |
| 72 | } |
| 73 | @@ -352,8 +372,20 @@ static void mt7996_dma_enable(struct mt7996_dev *dev, bool reset) |
| 74 | WF_WFDMA0_GLO_CFG_EXT1_TX_FCTRL_MODE); |
| 75 | |
| 76 | mt76_set(dev, MT_WFDMA_HOST_CONFIG, |
| 77 | - MT_WFDMA_HOST_CONFIG_PDMA_BAND | |
| 78 | - MT_WFDMA_HOST_CONFIG_BAND2_PCIE1); |
| 79 | + MT_WFDMA_HOST_CONFIG_PDMA_BAND); |
| 80 | + |
| 81 | + mt76_clear(dev, MT_WFDMA_HOST_CONFIG, |
| 82 | + MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 | |
| 83 | + MT_WFDMA_HOST_CONFIG_BAND1_PCIE1 | |
| 84 | + MT_WFDMA_HOST_CONFIG_BAND2_PCIE1); |
| 85 | + |
| 86 | + if (dev->option_type == 2) |
| 87 | + mt76_set(dev, MT_WFDMA_HOST_CONFIG, |
| 88 | + MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 | |
| 89 | + MT_WFDMA_HOST_CONFIG_BAND1_PCIE1); |
| 90 | + else |
| 91 | + mt76_set(dev, MT_WFDMA_HOST_CONFIG, |
| 92 | + MT_WFDMA_HOST_CONFIG_BAND2_PCIE1); |
| 93 | |
| 94 | if (mtk_wed_device_active(&dev->mt76.mmio.wed) && |
| 95 | is_mt7992(&dev->mt76)) { |
| 96 | @@ -366,6 +398,15 @@ static void mt7996_dma_enable(struct mt7996_dev *dev, bool reset) |
| 97 | mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL, |
| 98 | MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK, 0x14); |
| 99 | |
| 100 | + if (dev->hif2->speed < PCIE_SPEED_8_0GT || |
| 101 | + (dev->hif2->speed == PCIE_SPEED_8_0GT && dev->hif2->width < 2)) { |
| 102 | + mt76_rmw(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs, |
| 103 | + WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, |
| 104 | + FIELD_PREP(WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK, 0x3)); |
| 105 | + mt76_rmw(dev, MT_WFDMA_AXI_R2A_CTRL2, |
| 106 | + MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, |
| 107 | + FIELD_PREP(MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK, 0x3)); |
| 108 | + } |
| 109 | /* WFDMA rx threshold */ |
| 110 | mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_45_TH + hif1_ofs, 0xc000c); |
| 111 | mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_67_TH + hif1_ofs, 0x10008); |
| 112 | diff --git a/mt7996/init.c b/mt7996/init.c |
| 113 | index 90f3a417..85fedca6 100644 |
| 114 | --- a/mt7996/init.c |
| 115 | +++ b/mt7996/init.c |
| 116 | @@ -500,7 +500,7 @@ static void mt7996_mac_init_basic_rates(struct mt7996_dev *dev) |
| 117 | void mt7996_mac_init(struct mt7996_dev *dev) |
| 118 | { |
| 119 | #define HIF_TXD_V2_1 0x21 |
| 120 | - int i; |
| 121 | + int i, rx_path_type, rro_bypass, txfree_path; |
| 122 | |
| 123 | mt76_clear(dev, MT_MDP_DCR2, MT_MDP_DCR2_RX_TRANS_SHORT); |
| 124 | |
| 125 | @@ -514,22 +514,45 @@ void mt7996_mac_init(struct mt7996_dev *dev) |
| 126 | } |
| 127 | |
| 128 | /* rro module init */ |
| 129 | - if (is_mt7996(&dev->mt76)) |
| 130 | - mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, 2); |
| 131 | - else |
| 132 | - mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, |
| 133 | - dev->hif2 ? 7 : 0); |
| 134 | + switch (dev->option_type) { |
| 135 | + case 2: |
| 136 | + /* eagle + 7988d */ |
| 137 | + rx_path_type = 3; |
| 138 | + rro_bypass = dev->has_rro ? 1 : 3; |
| 139 | + txfree_path = dev->has_rro ? 0 : 1; |
| 140 | + break; |
| 141 | + case 3: |
| 142 | + /* eagle + Airoha */ |
| 143 | + rx_path_type = 6; |
| 144 | + rro_bypass = dev->has_rro ? 1 : 3; |
| 145 | + txfree_path = dev->has_rro ? 0 : 1; |
| 146 | + break; |
| 147 | + case 4: |
| 148 | + /* Bollinger */ |
| 149 | + rx_path_type = 2; |
| 150 | + rro_bypass = dev->has_rro ? 1 : 3; |
| 151 | + txfree_path = dev->has_rro ? 0 : 1; |
| 152 | + break; |
| 153 | + default: |
| 154 | + if (is_mt7996(&dev->mt76)) |
| 155 | + rx_path_type = 2; |
| 156 | + else |
| 157 | + rx_path_type = 7; |
| 158 | + |
| 159 | + rro_bypass = dev->has_rro ? 1 : 3; |
| 160 | + txfree_path = dev->has_rro ? 0 : 1; |
| 161 | + break; |
| 162 | + } |
| 163 | + |
| 164 | + mt7996_mcu_set_rro(dev, UNI_RRO_SET_PLATFORM_TYPE, dev->hif2 ? rx_path_type : 0); |
| 165 | + mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, rro_bypass); |
| 166 | + mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, txfree_path); |
| 167 | |
| 168 | if (dev->has_rro) { |
| 169 | u16 timeout; |
| 170 | |
| 171 | timeout = mt76_rr(dev, MT_HW_REV) == MT_HW_REV1 ? 512 : 128; |
| 172 | mt7996_mcu_set_rro(dev, UNI_RRO_SET_FLUSH_TIMEOUT, timeout); |
| 173 | - mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 1); |
| 174 | - mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 0); |
| 175 | - } else { |
| 176 | - mt7996_mcu_set_rro(dev, UNI_RRO_SET_BYPASS_MODE, 3); |
| 177 | - mt7996_mcu_set_rro(dev, UNI_RRO_SET_TXFREE_PATH, 1); |
| 178 | } |
| 179 | |
| 180 | mt7996_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(SET), |
| 181 | @@ -607,9 +630,22 @@ static int mt7996_register_phy(struct mt7996_dev *dev, struct mt7996_phy *phy, |
| 182 | if (phy) |
| 183 | return 0; |
| 184 | |
| 185 | - if (is_mt7996(&dev->mt76) && band == MT_BAND2 && dev->hif2) { |
| 186 | - hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); |
| 187 | - wed = &dev->mt76.mmio.wed_hif2; |
| 188 | + if (is_mt7996(&dev->mt76) && dev->hif2) { |
| 189 | + switch (dev->option_type) { |
| 190 | + case 2: |
| 191 | + /* eagle + 7988d */ |
| 192 | + if (band == MT_BAND1) { |
| 193 | + hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); |
| 194 | + wed = &dev->mt76.mmio.wed_hif2; |
| 195 | + } |
| 196 | + break; |
| 197 | + default: |
| 198 | + if (band == MT_BAND2) { |
| 199 | + hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0); |
| 200 | + wed = &dev->mt76.mmio.wed_hif2; |
| 201 | + } |
| 202 | + break; |
| 203 | + } |
| 204 | } |
| 205 | |
| 206 | mphy = mt76_alloc_phy(&dev->mt76, sizeof(*phy), &mt7996_ops, band); |
| 207 | @@ -1048,6 +1084,9 @@ int mt7996_get_chip_sku(struct mt7996_dev *dev) |
| 208 | static int mt7996_init_hardware(struct mt7996_dev *dev) |
| 209 | { |
| 210 | int ret, idx; |
| 211 | + struct device_node *np = dev->mt76.dev->of_node; |
| 212 | + |
| 213 | + of_property_read_u32(np, "option_type", &dev->option_type); |
| 214 | |
| 215 | mt76_wr(dev, MT_INT_SOURCE_CSR, ~0); |
| 216 | if (is_mt7992(&dev->mt76)) { |
| 217 | diff --git a/mt7996/main.c b/mt7996/main.c |
| 218 | index e1c107fb..fd6fd78b 100644 |
| 219 | --- a/mt7996/main.c |
| 220 | +++ b/mt7996/main.c |
| 221 | @@ -1583,8 +1583,19 @@ mt7996_net_fill_forward_path(struct ieee80211_hw *hw, |
| 222 | struct mt7996_phy *phy = mt7996_hw_phy(hw); |
| 223 | struct mtk_wed_device *wed = &dev->mt76.mmio.wed; |
| 224 | |
| 225 | - if (phy != &dev->phy && phy->mt76->band_idx == MT_BAND2) |
| 226 | - wed = &dev->mt76.mmio.wed_hif2; |
| 227 | + if (phy != &dev->phy && dev->hif2) { |
| 228 | + switch (dev->option_type) { |
| 229 | + case 2: |
| 230 | + /* eagle + 7988d */ |
| 231 | + if (phy->mt76->band_idx == MT_BAND1) |
| 232 | + wed = &dev->mt76.mmio.wed_hif2; |
| 233 | + break; |
| 234 | + default: |
| 235 | + if (phy->mt76->band_idx == MT_BAND2) |
| 236 | + wed = &dev->mt76.mmio.wed_hif2; |
| 237 | + break; |
| 238 | + } |
| 239 | + } |
| 240 | |
| 241 | if (!mtk_wed_device_active(wed)) |
| 242 | return -ENODEV; |
| 243 | diff --git a/mt7996/mt7996.h b/mt7996/mt7996.h |
| 244 | index 6ea024ef..2ca6e55d 100644 |
| 245 | --- a/mt7996/mt7996.h |
| 246 | +++ b/mt7996/mt7996.h |
| 247 | @@ -8,6 +8,7 @@ |
| 248 | |
| 249 | #include <linux/interrupt.h> |
| 250 | #include <linux/ktime.h> |
| 251 | +#include <linux/pci.h> |
| 252 | #include "../mt76_connac.h" |
| 253 | #include "regs.h" |
| 254 | |
| 255 | @@ -350,6 +351,8 @@ struct mt7996_hif { |
| 256 | struct device *dev; |
| 257 | void __iomem *regs; |
| 258 | int irq; |
| 259 | + enum pci_bus_speed speed; |
| 260 | + enum pcie_link_width width; |
| 261 | }; |
| 262 | |
| 263 | struct mt7996_scs_ctrl { |
| 264 | @@ -574,6 +577,8 @@ struct mt7996_dev { |
| 265 | u8 eeprom_mode; |
| 266 | u32 bg_nxt_freq; |
| 267 | |
| 268 | + u32 option_type; |
| 269 | + |
| 270 | bool ibf; |
| 271 | u8 fw_debug_wm; |
| 272 | u8 fw_debug_wa; |
| 273 | diff --git a/mt7996/pci.c b/mt7996/pci.c |
| 274 | index f0d3f199..24d69d4d 100644 |
| 275 | --- a/mt7996/pci.c |
| 276 | +++ b/mt7996/pci.c |
| 277 | @@ -5,7 +5,6 @@ |
| 278 | |
| 279 | #include <linux/kernel.h> |
| 280 | #include <linux/module.h> |
| 281 | -#include <linux/pci.h> |
| 282 | |
| 283 | #include "mt7996.h" |
| 284 | #include "mac.h" |
| 285 | @@ -93,6 +92,7 @@ static int mt7996_pci_hif2_probe(struct pci_dev *pdev) |
| 286 | hif->dev = &pdev->dev; |
| 287 | hif->regs = pcim_iomap_table(pdev)[0]; |
| 288 | hif->irq = pdev->irq; |
| 289 | + pcie_bandwidth_available(pdev, NULL, &hif->speed, &hif->width); |
| 290 | spin_lock_bh(&hif_lock); |
| 291 | list_add(&hif->list, &hif_list); |
| 292 | spin_unlock_bh(&hif_lock); |
| 293 | diff --git a/mt7996/regs.h b/mt7996/regs.h |
| 294 | index 476b23c3..050637c1 100644 |
| 295 | --- a/mt7996/regs.h |
| 296 | +++ b/mt7996/regs.h |
| 297 | @@ -435,6 +435,7 @@ enum offs_rev { |
| 298 | #define WF_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0) |
| 299 | #define WF_WFDMA0_GLO_CFG_EXT0_RX_WB_RXD BIT(18) |
| 300 | #define WF_WFDMA0_GLO_CFG_EXT0_WED_MERGE_MODE BIT(14) |
| 301 | +#define WF_WFDMA0_GLO_CFG_EXT0_OUTSTAND_MASK GENMASK(27, 24) |
| 302 | |
| 303 | #define WF_WFDMA0_GLO_CFG_EXT1 MT_WFDMA0(0x2b4) |
| 304 | #define WF_WFDMA0_GLO_CFG_EXT1_CALC_MODE BIT(31) |
| 305 | @@ -454,6 +455,7 @@ enum offs_rev { |
| 306 | |
| 307 | #define MT_WFDMA_HOST_CONFIG MT_WFDMA_EXT_CSR(0x30) |
| 308 | #define MT_WFDMA_HOST_CONFIG_PDMA_BAND BIT(0) |
| 309 | +#define MT_WFDMA_HOST_CONFIG_BAND0_PCIE1 BIT(20) |
| 310 | #define MT_WFDMA_HOST_CONFIG_BAND1_PCIE1 BIT(21) |
| 311 | #define MT_WFDMA_HOST_CONFIG_BAND2_PCIE1 BIT(22) |
| 312 | |
| 313 | @@ -463,6 +465,9 @@ enum offs_rev { |
| 314 | #define MT_WFDMA_AXI_R2A_CTRL MT_WFDMA_EXT_CSR(0x500) |
| 315 | #define MT_WFDMA_AXI_R2A_CTRL_OUTSTAND_MASK GENMASK(4, 0) |
| 316 | |
| 317 | +#define MT_WFDMA_AXI_R2A_CTRL2 MT_WFDMA_EXT_CSR(0x508) |
| 318 | +#define MT_WFDMA_AXI_R2A_CTRL2_OUTSTAND_MASK GENMASK(31, 28) |
| 319 | + |
| 320 | #define MT_PCIE_RECOG_ID 0xd7090 |
| 321 | #define MT_PCIE_RECOG_ID_MASK GENMASK(30, 0) |
| 322 | #define MT_PCIE_RECOG_ID_SEM BIT(31) |
| 323 | -- |
| 324 | 2.18.0 |
| 325 | |