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71From: <chuanjia.liu@mediatek.com>
72To: <robh+dt@kernel.org>, <ryder.lee@mediatek.com>, <matthias.bgg@gmail.com>
73Subject: [PATCH v2 2/4] PCI: mediatek: Use regmap to get shared pcie-cfg base
74Date: Thu, 28 May 2020 14:16:46 +0800
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115Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
116 srv_heupstream@mediatek.com, "chuanjia.liu" <Chuanjia.Liu@mediatek.com>,
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124
125From: "chuanjia.liu" <Chuanjia.Liu@mediatek.com>
126
127Use regmap to get shared pcie-cfg base and change
128the method to get pcie irq.
129
130Signed-off-by: chuanjia.liu <Chuanjia.Liu@mediatek.com>
131---
132 drivers/pci/controller/pcie-mediatek.c | 25 ++++++++++++++++++-------
133 1 file changed, 18 insertions(+), 7 deletions(-)
134
135--- a/drivers/pci/controller/pcie-mediatek.c
136+++ b/drivers/pci/controller/pcie-mediatek.c
137@@ -14,6 +14,7 @@
138 #include <linux/irqchip/chained_irq.h>
139 #include <linux/irqdomain.h>
140 #include <linux/kernel.h>
141+#include <linux/mfd/syscon.h>
142 #include <linux/msi.h>
143 #include <linux/module.h>
144 #include <linux/of_address.h>
145@@ -23,6 +24,7 @@
146 #include <linux/phy/phy.h>
147 #include <linux/platform_device.h>
148 #include <linux/pm_runtime.h>
149+#include <linux/regmap.h>
150 #include <linux/reset.h>
151
152 #include "../pci.h"
153@@ -205,6 +207,7 @@ struct mtk_pcie_port {
154 * struct mtk_pcie - PCIe host information
155 * @dev: pointer to PCIe device
156 * @base: IO mapped register base
157+ * @cfg: IO mapped register map for PCIe config
158 * @free_ck: free-run reference clock
159 * @mem: non-prefetchable memory resource
160 * @ports: pointer to PCIe port information
161@@ -214,6 +217,7 @@ struct mtk_pcie_port {
162 struct mtk_pcie {
163 struct device *dev;
164 void __iomem *base;
165+ struct regmap *cfg;
166 struct clk *free_ck;
167
168 struct resource mem;
169@@ -651,7 +655,7 @@ static int mtk_pcie_setup_irq(struct mtk
170 return err;
171 }
172
173- port->irq = platform_get_irq(pdev, port->slot);
174+ port->irq = platform_get_irq_byname(pdev, "pcie_irq");
175 irq_set_chained_handler_and_data(port->irq,
176 mtk_pcie_intr_handler, port);
177
178@@ -666,12 +670,11 @@ static int mtk_pcie_startup_port_v2(stru
179 u32 val;
180 int err;
181
182- /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
183- if (pcie->base) {
184- val = readl(pcie->base + PCIE_SYS_CFG_V2);
185- val |= PCIE_CSR_LTSSM_EN(port->slot) |
186- PCIE_CSR_ASPM_L1_EN(port->slot);
187- writel(val, pcie->base + PCIE_SYS_CFG_V2);
188+ /* MT7622/MT7629 platforms need to enable LTSSM and ASPM. */
189+ if (pcie->cfg) {
190+ val = PCIE_CSR_LTSSM_EN(port->slot) |
191+ PCIE_CSR_ASPM_L1_EN(port->slot);
192+ regmap_update_bits(pcie->cfg, PCIE_SYS_CFG_V2, val, val);
193 }
194
195 /* Assert all reset signals */
196@@ -977,6 +980,7 @@ static int mtk_pcie_subsys_powerup(struc
197 struct device *dev = pcie->dev;
198 struct platform_device *pdev = to_platform_device(dev);
199 struct resource *regs;
200+ struct device_node *cfg_node;
201 int err;
202
203 /* get shared registers, which are optional */
204@@ -989,6 +993,13 @@ static int mtk_pcie_subsys_powerup(struc
205 }
206 }
207
208+ cfg_node = of_parse_phandle(dev->of_node, "mediatek,pcie-cfg", 0);
209+ if (cfg_node) {
210+ pcie->cfg = syscon_node_to_regmap(cfg_node);
211+ if (IS_ERR(pcie->cfg))
212+ return PTR_ERR(pcie->cfg);
213+ }
214+
215 pcie->free_ck = devm_clk_get(dev, "free_ck");
216 if (IS_ERR(pcie->free_ck)) {
217 if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)