blob: d5c42df65990709e4e8d23a4cbe4dc1e0554acaa [file] [log] [blame]
developerd0c89452024-10-11 16:53:27 +08001From eaaf030c560747704321c51c00e275da3d7a8217 Mon Sep 17 00:00:00 2001
2From: Howard Hsu <howard-yh.hsu@mediatek.com>
3Date: Tue, 3 Sep 2024 15:36:56 +0800
4Subject: [PATCH 191/223] mtk: mt76: mt7996: fix the capability of reception of
5 EHT MU PPDU
6
7This commit includes two changes. First, enable "EHT MU PPDU With 4x
8EHT-LTF And 0.8us GI" in EHT Phy capabilities element since hardware
9can support. Second, fix the value of "Maximum number of supported
10EHT LTFs" in the same element, where the previous setting of 3 in
11Bit 3-4 was incorrect.
12
13Signed-off-by: Howard Hsu <howard-yh.hsu@mediatek.com>
14
15---
16 mt7996/init.c | 5 ++---
17 1 file changed, 2 insertions(+), 3 deletions(-)
18
19diff --git a/mt7996/init.c b/mt7996/init.c
20index f739afd2..2db4b3b5 100644
21--- a/mt7996/init.c
22+++ b/mt7996/init.c
23@@ -1636,21 +1636,20 @@ mt7996_init_eht_caps(struct mt7996_phy *phy, enum nl80211_band band,
24 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK;
25
26 eht_cap_elem->phy_cap_info[4] =
27+ IEEE80211_EHT_PHY_CAP4_EHT_MU_PPDU_4_EHT_LTF_08_GI |
28 u8_encode_bits(min_t(int, sts - 1, 2),
29 IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
30
31 eht_cap_elem->phy_cap_info[5] =
32 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_16US,
33 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK) |
34- u8_encode_bits(u8_get_bits(0x11, GENMASK(1, 0)),
35+ u8_encode_bits(u8_get_bits(1, GENMASK(1, 0)),
36 IEEE80211_EHT_PHY_CAP5_MAX_NUM_SUPP_EHT_LTF_MASK);
37
38 val = width == NL80211_CHAN_WIDTH_320 ? 0xf :
39 width == NL80211_CHAN_WIDTH_160 ? 0x7 :
40 width == NL80211_CHAN_WIDTH_80 ? 0x3 : 0x1;
41 eht_cap_elem->phy_cap_info[6] =
42- u8_encode_bits(u8_get_bits(0x11, GENMASK(4, 2)),
43- IEEE80211_EHT_PHY_CAP6_MAX_NUM_SUPP_EHT_LTF_MASK) |
44 u8_encode_bits(val, IEEE80211_EHT_PHY_CAP6_MCS15_SUPP_MASK);
45
46 val = u8_encode_bits(nss, IEEE80211_EHT_MCS_NSS_RX) |
47--
482.45.2
49