blob: a97824b8cf4e38019ea8ce5509e2328429580203 [file] [log] [blame]
developerd0c89452024-10-11 16:53:27 +08001From 1836ddf781e91b41f66a1add7110bd24d133817c Mon Sep 17 00:00:00 2001
developer66e89bc2024-04-23 14:50:01 +08002From: StanleyYP Wang <StanleyYP.Wang@mediatek.com>
3Date: Mon, 11 Sep 2023 14:43:07 +0800
developerd0c89452024-10-11 16:53:27 +08004Subject: [PATCH 040/223] mtk: mt76: mt7996: add channel 68 & 96
developer66e89bc2024-04-23 14:50:01 +08005
developer66e89bc2024-04-23 14:50:01 +08006---
7 mac80211.c | 9 +++++++++
8 mt7996/eeprom.c | 49 +++++++++++++++++++++++++++++++++++++++++++++--
9 mt7996/eeprom.h | 2 ++
10 mt7996/mcu.c | 10 +++++++++-
11 mt7996/testmode.c | 15 ++++++++++++---
12 mt7996/testmode.h | 6 +++---
13 6 files changed, 82 insertions(+), 9 deletions(-)
14
15diff --git a/mac80211.c b/mac80211.c
developerd0c89452024-10-11 16:53:27 +080016index 1d2477d6..ee5aa608 100644
developer66e89bc2024-04-23 14:50:01 +080017--- a/mac80211.c
18+++ b/mac80211.c
19@@ -34,6 +34,15 @@ static const struct ieee80211_channel mt76_channels_5ghz[] = {
20 CHAN5G(60, 5300),
21 CHAN5G(64, 5320),
22
23+ CHAN5G(68, 5340),
24+ CHAN5G(72, 5360),
25+ CHAN5G(76, 5380),
26+ CHAN5G(80, 5400),
27+ CHAN5G(84, 5420),
28+ CHAN5G(88, 5440),
29+ CHAN5G(92, 5460),
30+ CHAN5G(96, 5480),
31+
32 CHAN5G(100, 5500),
33 CHAN5G(104, 5520),
34 CHAN5G(108, 5540),
35diff --git a/mt7996/eeprom.c b/mt7996/eeprom.c
developerd0c89452024-10-11 16:53:27 +080036index da30be33..b71961d9 100644
developer66e89bc2024-04-23 14:50:01 +080037--- a/mt7996/eeprom.c
38+++ b/mt7996/eeprom.c
39@@ -18,6 +18,17 @@ const struct ieee80211_channel dpd_2g_ch_list_bw20[] = {
40 CHAN2G(11, 2462)
41 };
42
43+const struct ieee80211_channel dpd_5g_skip_ch_list[] = {
44+ CHAN5G(68, 5340),
45+ CHAN5G(72, 5360),
46+ CHAN5G(76, 5380),
47+ CHAN5G(80, 5400),
48+ CHAN5G(84, 5420),
49+ CHAN5G(88, 5440),
50+ CHAN5G(92, 5460),
51+ CHAN5G(96, 5480)
52+};
53+
54 const struct ieee80211_channel dpd_5g_ch_list_bw160[] = {
55 CHAN5G(50, 5250),
56 CHAN5G(114, 5570),
57@@ -44,6 +55,7 @@ const struct ieee80211_channel dpd_6g_ch_list_bw320[] = {
58 };
59
60 const u32 dpd_2g_bw20_ch_num = ARRAY_SIZE(dpd_2g_ch_list_bw20);
61+const u32 dpd_5g_skip_ch_num = ARRAY_SIZE(dpd_5g_skip_ch_list);
62 const u32 dpd_5g_bw160_ch_num = ARRAY_SIZE(dpd_5g_ch_list_bw160);
63 const u32 dpd_6g_bw160_ch_num = ARRAY_SIZE(dpd_6g_ch_list_bw160);
64 const u32 dpd_6g_bw320_ch_num = ARRAY_SIZE(dpd_6g_ch_list_bw320);
developerd0c89452024-10-11 16:53:27 +080065@@ -191,8 +203,8 @@ mt7996_get_dpd_per_band_size(struct mt7996_dev *dev, enum nl80211_band band)
developer66e89bc2024-04-23 14:50:01 +080066 if (band == NL80211_BAND_2GHZ)
67 dpd_size = dpd_2g_bw20_ch_num * DPD_PER_CH_BW20_SIZE;
68 else if (band == NL80211_BAND_5GHZ)
69- dpd_size = mphy->sband_5g.sband.n_channels * DPD_PER_CH_BW20_SIZE +
70- dpd_5g_bw160_ch_num * DPD_PER_CH_GT_BW20_SIZE;
71+ dpd_size = (mphy->sband_5g.sband.n_channels - dpd_5g_skip_ch_num) *
72+ DPD_PER_CH_BW20_SIZE + dpd_5g_bw160_ch_num * DPD_PER_CH_GT_BW20_SIZE;
73 else
74 dpd_size = mphy->sband_6g.sband.n_channels * DPD_PER_CH_BW20_SIZE +
75 (dpd_6g_bw160_ch_num + dpd_6g_bw320_ch_num) * DPD_PER_CH_GT_BW20_SIZE;
developerd0c89452024-10-11 16:53:27 +080076@@ -481,6 +493,39 @@ out:
developer66e89bc2024-04-23 14:50:01 +080077 return ret;
78 }
79
80+static void mt7996_eeprom_init_precal(struct mt7996_dev *dev)
81+{
82+#define MT76_CHANNELS_5GHZ_SIZE 36 /* ARRAY_SIZE(mt76_channels_5ghz) */
83+#define MT76_CHANNELS_6GHZ_SIZE 59 /* ARRAY_SIZE(mt76_channels_6ghz) */
84+
85+ dev->prek.dpd_ch_num[DPD_CH_NUM_BW20_2G] = ARRAY_SIZE(dpd_2g_ch_list_bw20);
86+ dev->prek.dpd_ch_num[DPD_CH_NUM_BW20_5G_SKIP] = ARRAY_SIZE(dpd_5g_skip_ch_list);
87+ dev->prek.dpd_ch_num[DPD_CH_NUM_BW20_5G] = MT76_CHANNELS_5GHZ_SIZE -
88+ DPD_CH_NUM(BW20_5G_SKIP);
89+ dev->prek.dpd_ch_num[DPD_CH_NUM_BW160_5G] = ARRAY_SIZE(dpd_5g_ch_list_bw160);
90+ dev->prek.dpd_ch_num[DPD_CH_NUM_BW20_6G] = MT76_CHANNELS_6GHZ_SIZE;
91+ dev->prek.dpd_ch_num[DPD_CH_NUM_BW160_6G] = ARRAY_SIZE(dpd_6g_ch_list_bw160);
92+
93+ switch (mt76_chip(&dev->mt76)) {
94+ case 0x7990:
95+ dev->prek.rev = mt7996_prek_rev;
96+ /* 5g & 6g bw 80 dpd channel list is not used */
97+ dev->prek.dpd_ch_num[DPD_CH_NUM_BW320_6G] = ARRAY_SIZE(dpd_6g_ch_list_bw320);
98+ break;
99+ case 0x7992:
100+ dev->prek.rev = mt7992_prek_rev;
101+ dev->prek.dpd_ch_num[DPD_CH_NUM_BW80_5G] = ARRAY_SIZE(dpd_5g_ch_list_bw80);
102+ /* 6g is not used in current sku */
103+ dev->prek.dpd_ch_num[DPD_CH_NUM_BW20_6G] = 0;
104+ dev->prek.dpd_ch_num[DPD_CH_NUM_BW80_6G] = 0;
105+ dev->prek.dpd_ch_num[DPD_CH_NUM_BW160_6G] = 0;
106+ break;
107+ default:
108+ dev->prek.rev = mt7996_prek_rev;
109+ break;
110+ }
111+}
112+
113 static int mt7996_eeprom_load_precal(struct mt7996_dev *dev)
114 {
115 struct mt76_dev *mdev = &dev->mt76;
116diff --git a/mt7996/eeprom.h b/mt7996/eeprom.h
developerd0c89452024-10-11 16:53:27 +0800117index e90180a0..782d847b 100644
developer66e89bc2024-04-23 14:50:01 +0800118--- a/mt7996/eeprom.h
119+++ b/mt7996/eeprom.h
120@@ -67,6 +67,8 @@ enum mt7996_eeprom_field {
121
122 extern const struct ieee80211_channel dpd_2g_ch_list_bw20[];
123 extern const u32 dpd_2g_bw20_ch_num;
124+extern const struct ieee80211_channel dpd_5g_skip_ch_list[];
125+extern const u32 dpd_5g_skip_ch_num;
126 extern const struct ieee80211_channel dpd_5g_ch_list_bw160[];
127 extern const u32 dpd_5g_bw160_ch_num;
128 extern const struct ieee80211_channel dpd_6g_ch_list_bw160[];
129diff --git a/mt7996/mcu.c b/mt7996/mcu.c
developerd0c89452024-10-11 16:53:27 +0800130index 9e548100..54a84966 100644
developer66e89bc2024-04-23 14:50:01 +0800131--- a/mt7996/mcu.c
132+++ b/mt7996/mcu.c
developerd0c89452024-10-11 16:53:27 +0800133@@ -3802,7 +3802,8 @@ int mt7996_mcu_apply_tx_dpd(struct mt7996_phy *phy)
developer66e89bc2024-04-23 14:50:01 +0800134 chan_list_size = mphy->sband_5g.sband.n_channels;
135 base_offset += dpd_size_2g;
136 if (bw == NL80211_CHAN_WIDTH_160) {
137- base_offset += mphy->sband_5g.sband.n_channels * DPD_PER_CH_BW20_SIZE;
138+ base_offset += (mphy->sband_5g.sband.n_channels - dpd_5g_skip_ch_num) *
139+ DPD_PER_CH_BW20_SIZE;
140 per_chan_size = DPD_PER_CH_GT_BW20_SIZE;
141 cal_id = RF_DPD_FLAT_5G_MEM_CAL;
142 chan_list = dpd_5g_ch_list_bw160;
developerd0c89452024-10-11 16:53:27 +0800143@@ -3811,6 +3812,9 @@ int mt7996_mcu_apply_tx_dpd(struct mt7996_phy *phy)
developer66e89bc2024-04-23 14:50:01 +0800144 /* apply (center channel - 2)'s dpd cal data for bw 40/80 channels */
145 channel -= 2;
146 }
147+ if (channel >= dpd_5g_skip_ch_list[0].hw_value &&
148+ channel <= dpd_5g_skip_ch_list[dpd_5g_skip_ch_num - 1].hw_value)
149+ return 0;
150 break;
151 case NL80211_BAND_6GHZ:
152 dpd_mask = MT_EE_WIFI_CAL_DPD_6G;
developerd0c89452024-10-11 16:53:27 +0800153@@ -3850,6 +3854,10 @@ int mt7996_mcu_apply_tx_dpd(struct mt7996_phy *phy)
developer66e89bc2024-04-23 14:50:01 +0800154 if (idx == chan_list_size)
155 return -EINVAL;
156
157+ if (band == NL80211_BAND_5GHZ && bw != NL80211_CHAN_WIDTH_160 &&
158+ channel > dpd_5g_skip_ch_list[dpd_5g_skip_ch_num - 1].hw_value)
159+ idx -= dpd_5g_skip_ch_num;
160+
161 cal += MT_EE_CAL_GROUP_SIZE + base_offset + idx * per_chan_size;
162
163 for (i = 0; i < per_chan_size / MT_EE_CAL_UNIT; i++) {
164diff --git a/mt7996/testmode.c b/mt7996/testmode.c
developerd0c89452024-10-11 16:53:27 +0800165index bace3afe..6de49afc 100644
developer66e89bc2024-04-23 14:50:01 +0800166--- a/mt7996/testmode.c
167+++ b/mt7996/testmode.c
developerd0c89452024-10-11 16:53:27 +0800168@@ -537,6 +537,11 @@ mt7996_tm_dpd_prek_send_req(struct mt7996_phy *phy, struct mt7996_tm_req *req,
developer66e89bc2024-04-23 14:50:01 +0800169 memcpy(&chandef_backup, chandef, sizeof(struct cfg80211_chan_def));
170
171 for (i = 0; i < channel_size; i++) {
172+ if (chan_list[i].band == NL80211_BAND_5GHZ &&
173+ chan_list[i].hw_value >= dpd_5g_skip_ch_list[0].hw_value &&
174+ chan_list[i].hw_value <= dpd_5g_skip_ch_list[dpd_5g_skip_ch_num - 1].hw_value)
175+ continue;
176+
177 memcpy(chandef->chan, &chan_list[i], sizeof(struct ieee80211_channel));
178 chandef->width = width;
179
developerd0c89452024-10-11 16:53:27 +0800180@@ -618,7 +623,8 @@ mt7996_tm_dpd_prek(struct mt7996_phy *phy, enum mt76_testmode_state state)
developer66e89bc2024-04-23 14:50:01 +0800181 NL80211_CHAN_WIDTH_20, RF_DPD_FLAT_5G_CAL);
182 if (ret)
183 return ret;
184- wait_on_prek_offset += mphy->sband_5g.sband.n_channels * DPD_PER_CH_BW20_SIZE;
185+ wait_on_prek_offset += (mphy->sband_5g.sband.n_channels - dpd_5g_skip_ch_num) *
186+ DPD_PER_CH_BW20_SIZE;
187 wait_event_timeout(mdev->mcu.wait,
188 dev->cur_prek_offset == wait_on_prek_offset, 30 * HZ);
189
developerd0c89452024-10-11 16:53:27 +0800190@@ -874,6 +880,7 @@ mt7996_tm_get_center_chan(struct mt7996_phy *phy, struct cfg80211_chan_def *chan
developer66e89bc2024-04-23 14:50:01 +0800191 const struct ieee80211_channel *chan = mphy->sband_5g.sband.channels;
192 u32 bitmap, i, offset, width_mhz, size = mphy->sband_5g.sband.n_channels;
193 u16 first_control = 0, control_chan = chandef->chan->hw_value;
194+ bool not_first;
195
196 bitmap = mt7996_tm_bw_mapping(chandef->width, BW_MAP_NL_TO_CONTROL_BITMAP_5G);
197 if (!bitmap)
developerd0c89452024-10-11 16:53:27 +0800198@@ -883,7 +890,9 @@ mt7996_tm_get_center_chan(struct mt7996_phy *phy, struct cfg80211_chan_def *chan
developer66e89bc2024-04-23 14:50:01 +0800199 offset = width_mhz / 10 - 2;
200
201 for (i = 0; i < size; i++) {
202- if (!((1 << i) & bitmap))
203+ not_first = (chandef->width != NL80211_CHAN_WIDTH_160) ?
204+ (i % bitmap) : (i >= 32) || !((1 << i) & bitmap);
205+ if (not_first)
206 continue;
207
208 if (control_chan >= chan[i].hw_value)
developerd0c89452024-10-11 16:53:27 +0800209@@ -892,7 +901,7 @@ mt7996_tm_get_center_chan(struct mt7996_phy *phy, struct cfg80211_chan_def *chan
developer66e89bc2024-04-23 14:50:01 +0800210 break;
211 }
212
213- if (i == size || first_control == 0)
214+ if (first_control == 0)
215 return control_chan;
216
217 return first_control + offset;
218diff --git a/mt7996/testmode.h b/mt7996/testmode.h
developer05f3b2b2024-08-19 19:17:34 +0800219index f97ccb26..ba1767ae 100644
developer66e89bc2024-04-23 14:50:01 +0800220--- a/mt7996/testmode.h
221+++ b/mt7996/testmode.h
222@@ -38,9 +38,9 @@ enum {
223 BF_CDBW_8080MHZ,
224 };
225
226-#define FIRST_CONTROL_CHAN_BITMAP_BW40 0x5555555
227-#define FIRST_CONTROL_CHAN_BITMAP_BW80 0x111111
228-#define FIRST_CONTROL_CHAN_BITMAP_BW160 0x100101
229+#define FIRST_CONTROL_CHAN_BITMAP_BW40 2
230+#define FIRST_CONTROL_CHAN_BITMAP_BW80 4
231+#define FIRST_CONTROL_CHAN_BITMAP_BW160 0x10010101
232
233 enum bw_mapping_method {
234 BW_MAP_NL_TO_FW,
235--
developerd0c89452024-10-11 16:53:27 +08002362.45.2
developer66e89bc2024-04-23 14:50:01 +0800237